Lines Matching defs:CLKSEL_VALID
45 #define CLKSEL_VALID 1
122 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
123 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
124 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
130 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
131 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
132 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
138 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
139 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
140 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
146 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
147 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
148 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
154 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
155 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
156 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
157 [5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
163 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
164 [1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 },
165 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
166 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
172 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
173 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
174 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
175 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
176 [8] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL3, PLL_DIV1 },
182 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
183 [8] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
184 [9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
185 [12] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV1 },
186 [13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 },
192 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
193 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
199 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
200 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
201 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
202 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
209 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
210 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
211 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
213 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
214 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
215 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
217 { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
218 { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
219 { CLKSEL_VALID, CGA_PLL3, PLL_DIV4 },
225 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
226 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
227 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
229 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
230 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
231 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
237 { CLKSEL_VALID, CGB_PLL1, PLL_DIV1 },
238 { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
239 { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
241 { CLKSEL_VALID, CGB_PLL2, PLL_DIV1 },
242 { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
243 { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
249 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
250 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
251 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
257 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
258 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
259 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
260 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
261 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
263 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
264 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
270 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
271 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
272 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
273 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
274 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
276 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
277 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
283 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
284 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
285 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
286 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
287 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
289 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
290 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
296 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
297 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
298 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
299 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
300 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
302 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
303 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
311 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
312 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
315 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
316 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
323 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
325 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
333 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
334 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
335 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
336 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
337 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
338 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
345 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
346 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
347 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
350 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
357 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
358 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
359 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
360 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
362 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
363 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
370 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
371 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
372 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
373 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
375 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
376 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
382 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
384 [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
391 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
392 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
393 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
399 [6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
406 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
407 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
408 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
409 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
410 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
411 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
412 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
419 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
420 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
421 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
422 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
423 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
424 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
425 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
431 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
432 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
433 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
434 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
435 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
437 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
438 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
444 [2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
445 [3] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
446 [4] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
447 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
448 [6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
454 [2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
455 [3] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV3 },
456 [4] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
457 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
458 [6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
459 [7] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
874 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID))