Lines Matching defs:CGA_PLL1
28 #define CGA_PLL1 1
122 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
123 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
130 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
138 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
139 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
146 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
154 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
155 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
163 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
164 [1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 },
172 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
173 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
182 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
192 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
193 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
199 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
200 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
209 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
210 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
211 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
225 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
226 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
227 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
249 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
250 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
251 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
258 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
259 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
260 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
261 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
276 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
277 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
284 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
285 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
286 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
287 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
302 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
303 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
311 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
312 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
333 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
334 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
335 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
350 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
357 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
358 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
359 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
360 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
375 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
376 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
382 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
384 [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
391 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
392 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
393 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
399 [6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
406 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
407 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
408 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
409 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
424 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
425 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
432 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
433 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
434 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
435 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
1208 case CGA_PLL1:
1357 legacy_pll_init(np, CGA_PLL1 + idx);