Lines Matching refs:cdce
294 struct cdce706_dev_data *cdce = hwd->dev_data;
310 struct clk *gp_clk = cdce->clkin_clk[cdce->clkin[0].parent];
446 static int cdce706_register_hw(struct cdce706_dev_data *cdce,
456 hw->dev_data = cdce;
459 ret = devm_clk_hw_register(&cdce->client->dev,
462 dev_err(&cdce->client->dev, "Failed to register %s\n",
470 static int cdce706_register_clkin(struct cdce706_dev_data *cdce)
474 .parent_names = cdce->clkin_name,
475 .num_parents = ARRAY_SIZE(cdce->clkin_name),
481 for (i = 0; i < ARRAY_SIZE(cdce->clkin_name); ++i) {
482 struct clk *parent = devm_clk_get(&cdce->client->dev,
486 cdce->clkin_name[i] = cdce706_source_name[i];
488 cdce->clkin_name[i] = __clk_get_name(parent);
489 cdce->clkin_clk[i] = parent;
493 ret = cdce706_reg_read(cdce, CDCE706_CLKIN_SOURCE, &source);
498 ret = cdce706_reg_read(cdce, CDCE706_CLKIN_CLOCK, &clock);
501 cdce->clkin[0].parent = !!(clock & CDCE706_CLKIN_CLOCK_MASK);
504 ret = cdce706_register_hw(cdce, cdce->clkin,
505 ARRAY_SIZE(cdce->clkin),
510 static int cdce706_register_plls(struct cdce706_dev_data *cdce)
521 ret = cdce706_reg_read(cdce, CDCE706_PLL_MUX, &mux);
525 for (i = 0; i < ARRAY_SIZE(cdce->pll); ++i) {
528 ret = cdce706_reg_read(cdce, CDCE706_PLL_M_LOW(i), &m);
531 ret = cdce706_reg_read(cdce, CDCE706_PLL_N_LOW(i), &n);
534 ret = cdce706_reg_read(cdce, CDCE706_PLL_HI(i), &v);
537 cdce->pll[i].div = m | ((v & CDCE706_PLL_HI_M_MASK) << 8);
538 cdce->pll[i].mul = n | ((v & CDCE706_PLL_HI_N_MASK) <<
540 cdce->pll[i].mux = mux & CDCE706_PLL_MUX_MASK(i);
541 dev_dbg(&cdce->client->dev,
543 cdce->pll[i].div, cdce->pll[i].mul, cdce->pll[i].mux);
546 ret = cdce706_register_hw(cdce, cdce->pll,
547 ARRAY_SIZE(cdce->pll),
552 static int cdce706_register_dividers(struct cdce706_dev_data *cdce)
563 for (i = 0; i < ARRAY_SIZE(cdce->divider); ++i) {
566 ret = cdce706_reg_read(cdce, CDCE706_DIVIDER_PLL(i), &val);
569 cdce->divider[i].parent =
573 ret = cdce706_reg_read(cdce, CDCE706_DIVIDER(i), &val);
576 cdce->divider[i].div = val & CDCE706_DIVIDER_DIVIDER_MASK;
577 dev_dbg(&cdce->client->dev,
579 cdce->divider[i].parent, cdce->divider[i].div);
582 ret = cdce706_register_hw(cdce, cdce->divider,
583 ARRAY_SIZE(cdce->divider),
588 static int cdce706_register_clkouts(struct cdce706_dev_data *cdce)
599 for (i = 0; i < ARRAY_SIZE(cdce->clkout); ++i) {
602 ret = cdce706_reg_read(cdce, CDCE706_CLKOUT(i), &val);
605 cdce->clkout[i].parent = val & CDCE706_CLKOUT_DIVIDER_MASK;
606 dev_dbg(&cdce->client->dev,
608 cdce->clkout[i].parent);
611 return cdce706_register_hw(cdce, cdce->clkout,
612 ARRAY_SIZE(cdce->clkout),
619 struct cdce706_dev_data *cdce = data;
622 if (idx >= ARRAY_SIZE(cdce->clkout)) {
627 return &cdce->clkout[idx].hw;
634 struct cdce706_dev_data *cdce;
640 cdce = devm_kzalloc(&client->dev, sizeof(*cdce), GFP_KERNEL);
641 if (!cdce)
644 cdce->client = client;
645 cdce->regmap = devm_regmap_init_i2c(client, &cdce706_regmap_config);
646 if (IS_ERR(cdce->regmap)) {
651 i2c_set_clientdata(client, cdce);
653 ret = cdce706_register_clkin(cdce);
656 ret = cdce706_register_plls(cdce);
659 ret = cdce706_register_dividers(cdce);
662 ret = cdce706_register_clkouts(cdce);
666 cdce);