Lines Matching refs:reg
34 /* BG2/BG2CDs VCO_B has an additional shift of 4 for its VCO_CTRL0 reg */
116 u32 reg;
118 reg = readl_relaxed(vco->base + VCO_CTRL0);
120 reg >>= 4;
122 return !!(reg & VCO_POWERUP);
128 u32 reg;
130 reg = readl_relaxed(vco->base + VCO_CTRL0);
132 reg |= VCO_POWERUP << 4;
134 reg |= VCO_POWERUP;
135 writel_relaxed(reg, vco->base + VCO_CTRL0);
143 u32 reg;
145 reg = readl_relaxed(vco->base + VCO_CTRL0);
147 reg &= ~(VCO_POWERUP << 4);
149 reg &= ~VCO_POWERUP;
150 writel_relaxed(reg, vco->base + VCO_CTRL0);
159 u32 reg, refdiv, fbdiv;
163 reg = readl_relaxed(vco->base + VCO_CTRL1);
164 refdiv = (reg & VCO_REFDIV_MASK) >> VCO_REFDIV_SHIFT;
166 fbdiv = (reg & VCO_FBDIV_MASK) >> VCO_FBDIV_SHIFT;
215 u32 reg;
220 reg = readl_relaxed(ch->base + VCO_CTRL10);
221 reg &= VCO_POWERUP_CH1 << ch->index;
223 return !!reg;
229 u32 reg;
231 reg = readl_relaxed(ch->base + VCO_CTRL10);
232 reg |= VCO_POWERUP_CH1 << ch->index;
233 writel_relaxed(reg, ch->base + VCO_CTRL10);
241 u32 reg;
243 reg = readl_relaxed(ch->base + VCO_CTRL10);
244 reg &= ~(VCO_POWERUP_CH1 << ch->index);
245 writel_relaxed(reg, ch->base + VCO_CTRL10);
255 u32 reg, div_av2, div_av3, divider = 1;
258 reg = readl_relaxed(ch->base + VCO_CTRL30);
259 if ((reg & (VCO_DPLL_CH1_ENABLE << ch->index)) == 0)
267 reg = readl_relaxed(ch->base + VCO_SYNC1n(ch->index));
268 /* BG2/BG2CDs SYNC1 reg on AVPLL_B channel 1 is shifted by 4 */
270 reg >>= 4;
271 divider = reg & VCO_SYNC1_MASK;
273 reg = readl_relaxed(ch->base + VCO_SYNC2n(ch->index));
274 freq *= reg & VCO_SYNC2_MASK;
284 reg = readl_relaxed(ch->base + VCO_CTRL11) >> 7;
285 reg = (reg >> (ch->index * 3));
286 if (reg & BIT(2))
287 divider *= div_hdmi[reg & 0x3];
294 reg = readl_relaxed(ch->base + VCO_CTRL11);
295 reg >>= 28;
297 reg = readl_relaxed(ch->base + VCO_CTRL12);
298 reg >>= (ch->index-1) * 3;
300 if (reg & BIT(2))
301 divider *= div_av1[reg & 0x3];
308 reg = readl_relaxed(ch->base + VCO_CTRL12);
309 reg >>= 18 + (ch->index * 7);
311 reg = readl_relaxed(ch->base + VCO_CTRL13);
312 reg >>= (ch->index - 2) * 7;
314 reg = readl_relaxed(ch->base + VCO_CTRL14);
316 div_av2 = reg & 0x7f;
326 reg = readl_relaxed(ch->base + VCO_CTRL14);
327 reg >>= 7 + (ch->index * 4);
329 reg = readl_relaxed(ch->base + VCO_CTRL15);
331 div_av3 = reg & 0xf;