Lines Matching defs:divider
255 u32 reg, div_av2, div_av3, divider = 1;
271 divider = reg & VCO_SYNC1_MASK;
281 * HDMI divider start at VCO_CTRL11, bit 7; MSB is enable, lower 2 bit
282 * determine divider.
287 divider *= div_hdmi[reg & 0x3];
290 * AV1 divider start at VCO_CTRL11, bit 28; MSB is enable, lower 2 bit
291 * determine divider.
301 divider *= div_av1[reg & 0x3];
304 * AV2 divider start at VCO_CTRL12, bit 18; each 7 bits wide,
318 divider *= div_av2;
321 * AV3 divider start at VCO_CTRL14, bit 7; each 4 bits wide.
322 * AV2/AV3 form a fractional divider, where only specfic values for AV3
336 do_div(freq, divider);