Lines Matching defs:name
37 ccu->name, ccu_policy->enable.offset, limit);
43 ccu->name, ccu_policy->control.offset, limit);
86 const char *name;
92 name = bcm_clk->init_data.name;
102 __func__, name, policy->offset, limit);
112 __func__, name, gate->offset, limit);
120 name, hyst->offset, limit);
125 pr_err("%s: hysteresis but no gate for %s\n", __func__, name);
133 __func__, name, div->u.s.offset, limit);
143 __func__, name, div->u.s.offset, limit);
152 __func__, name, sel->offset, limit);
161 __func__, name, trig->offset, limit);
170 __func__, name, trig->offset, limit);
410 const char *name;
423 name = bcm_clk->init_data.name;
426 if (policy_exists(policy) && !policy_valid(policy, name))
430 if (gate_exists(gate) && !gate_valid(gate, "gate", name))
434 if (hyst_exists(hyst) && !hyst_valid(hyst, name))
439 if (!sel_valid(sel, "selector", name))
444 __func__, name);
452 if (!div_valid(div, "divider", name))
456 if (!div_valid(pre_div, "pre-divider", name))
460 name);
466 if (!trig_valid(trig, "trigger", name))
470 if (!trig_valid(trig, "pre-trigger", name)) {
476 __func__, name);
481 name);
485 name);
511 * position of each clock name in the original array.
574 * There is one parent name for each defined parent clock.
635 __func__, init_data->name, ret);
720 (int)bcm_clk->type, init_data->name);
727 init_data->name);
736 init_data->name, ret);
777 if (!ccu_policy_valid(ccu_policy, ccu->name))