Lines Matching defs:init
1315 struct clk_init_data init;
1318 memset(&init, 0, sizeof(init));
1321 init.parent_names = &cprman->real_parent_names[0];
1322 init.num_parents = 1;
1323 init.name = pll_data->name;
1324 init.ops = &bcm2835_pll_clk_ops;
1325 init.flags = pll_data->flags | CLK_IGNORE_UNUSED;
1333 pll->hw.init = &init;
1349 struct clk_init_data init;
1362 memset(&init, 0, sizeof(init));
1364 init.parent_names = ÷r_data->source_pll;
1365 init.num_parents = 1;
1366 init.name = divider_name;
1367 init.ops = &bcm2835_pll_divider_clk_ops;
1368 init.flags = divider_data->flags | CLK_IGNORE_UNUSED;
1379 divider->div.hw.init = &init;
1410 struct clk_init_data init;
1429 memset(&init, 0, sizeof(init));
1430 init.parent_names = parents;
1431 init.num_parents = clock_data->num_mux_parents;
1432 init.name = clock_data->name;
1433 init.flags = clock_data->flags | CLK_IGNORE_UNUSED;
1440 init.flags |= CLK_SET_RATE_PARENT;
1443 init.ops = &bcm2835_vpu_clock_clk_ops;
1445 init.ops = &bcm2835_clock_clk_ops;
1446 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
1452 init.flags &= ~CLK_IS_CRITICAL;
1461 clock->hw.init = &init;