Lines Matching defs:clock
8 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
10 * The clock tree on the 2835 has several levels. There's a root
22 * skip layers of the tree (for example, the pixel clock comes
23 * directly from the PLLH PIX channel without using a CM_*CTL clock
37 #include <dt-bindings/clock/bcm2835.h>
320 * Real names of cprman clock parents looked up through
322 * parent_names[] arrays for clock registration.
344 /* Does a cycle of measuring a clock through the TCNT clock, which may
721 /* Unmask the reference clock from the oscillator. */
911 * fake it by having some fixed shifts preceding it in the clock tree,
927 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
928 struct bcm2835_cprman *cprman = clock->cprman;
929 const struct bcm2835_clock_data *data = clock->data;
938 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
939 const struct bcm2835_clock_data *data = clock->data;
950 /* different clamping limits apply for a mash clock */
971 static unsigned long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
975 const struct bcm2835_clock_data *data = clock->data;
983 * the bits are populated in any given clock.
1001 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1002 struct bcm2835_cprman *cprman = clock->cprman;
1003 const struct bcm2835_clock_data *data = clock->data;
1011 return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
1014 static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)
1016 struct bcm2835_cprman *cprman = clock->cprman;
1017 const struct bcm2835_clock_data *data = clock->data;
1023 clk_hw_get_name(&clock->hw));
1032 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1033 struct bcm2835_cprman *cprman = clock->cprman;
1034 const struct bcm2835_clock_data *data = clock->data;
1042 bcm2835_clock_wait_busy(clock);
1047 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1048 struct bcm2835_cprman *cprman = clock->cprman;
1049 const struct bcm2835_clock_data *data = clock->data;
1058 /* Debug code to measure the clock once it's turned on to see
1075 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1076 struct bcm2835_cprman *cprman = clock->cprman;
1077 const struct bcm2835_clock_data *data = clock->data;
1086 * In principle it is recommended to stop/start the clock first,
1088 * clock this requirement should be take care of by the
1118 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1119 struct bcm2835_cprman *cprman = clock->cprman;
1120 const struct bcm2835_clock_data *data = clock->data;
1131 *avgrate = bcm2835_clock_rate_from_divisor(clock, *prate, *div);
1137 high = bcm2835_clock_rate_from_divisor(clock, *prate,
1140 low = bcm2835_clock_rate_from_divisor(clock, *prate,
1156 /* clamp to min divider of 2 if we're dealing with a mash clock */
1195 * Select parent clock that results in the closest but lower rate
1203 * Don't choose a PLLC-derived clock as our parent
1207 * prior notification to our clock consumer.
1236 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1237 struct bcm2835_cprman *cprman = clock->cprman;
1238 const struct bcm2835_clock_data *data = clock->data;
1247 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1248 struct bcm2835_cprman *cprman = clock->cprman;
1249 const struct bcm2835_clock_data *data = clock->data;
1269 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
1270 struct bcm2835_cprman *cprman = clock->cprman;
1271 const struct bcm2835_clock_data *data = clock->data;
1297 * The VPU clock can never be disabled (it doesn't have an ENABLE
1298 * bit), so it gets its own set of clock ops.
1409 struct bcm2835_clock *clock;
1417 * actual clock-output-name of the parent.
1448 /* If the clock wasn't actually enabled at boot, it's not
1455 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL);
1456 if (!clock)
1459 clock->cprman = cprman;
1460 clock->data = clock_data;
1461 clock->hw.init = &init;
1463 ret = devm_clk_hw_register(cprman->dev, &clock->hw);
1466 return &clock->hw;
1488 /* assignment helper macros for different clock types */
1544 * Restrict clock sources for the PCM peripheral to the oscillator and
1641 * (Compact Camera Port 2) transmitter clock.
1701 /* PLLB is used for the ARM's clock. */
1730 * PLLC is the core PLL, used to drive the core VPU clock.
1857 * PLLH is used to supply the pixel clock or the AUX clock for the
1912 /* One Time Programmable Memory clock. Maximum 10Mhz. */
1922 * Used for a 1Mhz clock for the system clocksource, and also used
1970 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
1990 * VPU clock. This doesn't have an enable bit, since it drives
2047 /* Arasan EMMC clock */
2057 /* EMMC2 clock (only available for BCM2711) */
2150 /* TV encoder clock. Only operating frequency is 108Mhz. */
2205 * non-stop vpu clock.
2215 * Permanently take a reference on the parent of the SDRAM clock.
2219 * periodically switches the SDRAM to using our CM clock to do PVT
2323 MODULE_DESCRIPTION("BCM2835 clock driver");