Lines Matching refs:gck
39 struct clk_generated *gck = to_clk_generated(hw);
43 __func__, gck->gckdiv, gck->parent_id);
45 spin_lock_irqsave(gck->lock, flags);
46 regmap_write(gck->regmap, gck->layout->offset,
47 (gck->id & gck->layout->pid_mask));
48 regmap_update_bits(gck->regmap, gck->layout->offset,
49 AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask |
50 gck->layout->cmd | AT91_PMC_PCR_GCKEN,
51 field_prep(gck->layout->gckcss_mask, gck->parent_id) |
52 gck->layout->cmd |
53 FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) |
55 spin_unlock_irqrestore(gck->lock, flags);
61 struct clk_generated *gck = to_clk_generated(hw);
64 spin_lock_irqsave(gck->lock, flags);
65 regmap_write(gck->regmap, gck->layout->offset,
66 (gck->id & gck->layout->pid_mask));
67 regmap_update_bits(gck->regmap, gck->layout->offset,
68 gck->layout->cmd | AT91_PMC_PCR_GCKEN,
69 gck->layout->cmd);
70 spin_unlock_irqrestore(gck->lock, flags);
75 struct clk_generated *gck = to_clk_generated(hw);
79 spin_lock_irqsave(gck->lock, flags);
80 regmap_write(gck->regmap, gck->layout->offset,
81 (gck->id & gck->layout->pid_mask));
82 regmap_read(gck->regmap, gck->layout->offset, &status);
83 spin_unlock_irqrestore(gck->lock, flags);
92 struct clk_generated *gck = to_clk_generated(hw);
94 return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1);
126 struct clk_generated *gck = to_clk_generated(hw);
136 if (gck->range.max && req->rate > gck->range.max)
137 req->rate = gck->range.max;
138 if (gck->range.min && req->rate < gck->range.min)
139 req->rate = gck->range.min;
142 if (gck->chg_pid == i)
152 (gck->range.max && min_rate > gck->range.max))
173 * that the only clks able to modify gck rate are those of audio IPs.
176 if (gck->chg_pid < 0)
179 parent = clk_hw_get_parent_by_index(hw, gck->chg_pid);
200 if (best_rate < 0 || (gck->range.max && best_rate > gck->range.max))
210 struct clk_generated *gck = to_clk_generated(hw);
215 if (gck->mux_table)
216 gck->parent_id = clk_mux_index_to_val(gck->mux_table, 0, index);
218 gck->parent_id = index;
225 struct clk_generated *gck = to_clk_generated(hw);
227 return gck->parent_id;
235 struct clk_generated *gck = to_clk_generated(hw);
241 if (gck->range.max && rate > gck->range.max)
248 gck->gckdiv = div - 1;
267 * @gck: Generated clock to set the startup parameters for.
272 static void clk_generated_startup(struct clk_generated *gck)
277 spin_lock_irqsave(gck->lock, flags);
278 regmap_write(gck->regmap, gck->layout->offset,
279 (gck->id & gck->layout->pid_mask));
280 regmap_read(gck->regmap, gck->layout->offset, &tmp);
281 spin_unlock_irqrestore(gck->lock, flags);
283 gck->parent_id = field_get(gck->layout->gckcss_mask, tmp);
284 gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp);
295 struct clk_generated *gck;
300 gck = kzalloc(sizeof(*gck), GFP_KERNEL);
301 if (!gck)
312 gck->id = id;
313 gck->hw.init = &init;
314 gck->regmap = regmap;
315 gck->lock = lock;
316 gck->range = *range;
317 gck->chg_pid = chg_pid;
318 gck->layout = layout;
319 gck->mux_table = mux_table;
321 clk_generated_startup(gck);
322 hw = &gck->hw;
323 ret = clk_hw_register(NULL, &gck->hw);
325 kfree(gck);