Lines Matching refs:post_divr_freq
69 * @post_divr_freq: input clock rate after the R divider
72 * on the input clock frequency after the post-R-divider @post_divr_freq.
79 static int __wrpll_calc_filter_range(unsigned long post_divr_freq)
81 if (post_divr_freq < MIN_POST_DIVR_FREQ ||
82 post_divr_freq > MAX_POST_DIVR_FREQ) {
84 __func__, post_divr_freq);
88 switch (post_divr_freq) {
226 u32 best_f, f, post_divr_freq;
277 post_divr_freq = div_u64(parent_rate, r);
278 vco_pre = fbdiv * post_divr_freq;
301 post_divr_freq = div_u64(parent_rate, best_r);
304 range = __wrpll_calc_filter_range(post_divr_freq);