Lines Matching refs:parent_rate
173 * @parent_rate: PLL input refclk rate (pre-R-divider)
184 unsigned long parent_rate)
188 if (parent_rate > MAX_INPUT_FREQ || parent_rate < MIN_POST_DIVR_FREQ)
191 c->parent_rate = parent_rate;
192 max_r_for_parent = div_u64(parent_rate, MIN_POST_DIVR_FREQ);
195 c->init_r = DIV_ROUND_UP_ULL(parent_rate, MAX_POST_DIVR_FREQ);
204 * @parent_rate: PLL input refclk rate (pre-R-divider)
222 unsigned long parent_rate)
236 if (parent_rate != c->parent_rate) {
237 if (__wrpll_update_parent_rate(c, parent_rate)) {
247 if (target_rate == parent_rate) {
261 ratio = div64_u64((target_vco_rate << ROUND_SHIFT), parent_rate);
277 post_divr_freq = div_u64(parent_rate, r);
301 post_divr_freq = div_u64(parent_rate, best_r);
315 * @parent_rate: PLL refclk rate
318 * PLL's input reference clock rate @parent_rate (before the R
331 unsigned long parent_rate)
342 n = parent_rate * fbdiv * (c->divf + 1);