Lines Matching defs:target_rate
130 * @target_rate: target PLL output clock rate
134 * target output rate @target_rate for the PLL. Along with returning the
144 static u8 __wrpll_calc_divq(u32 target_rate, u64 *vco_rate)
154 s = div_u64(MAX_VCO_FREQ, target_rate);
163 *vco_rate = (u64)target_rate << divq;
203 * @target_rate: target PLL output clock rate (post-Q-divider)
221 int wrpll_configure_for_rate(struct wrpll_cfg *c, u32 target_rate,
247 if (target_rate == parent_rate) {
255 divq = __wrpll_calc_divq(target_rate, &target_vco_rate);
290 delta = abs(target_rate - vco);