Lines Matching refs:OWL_DIVIDER_HW
223 OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
229 OWL_DIVIDER_HW(CMU_SICLK, 0, 4, 0, NULL),
259 OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, NULL),
283 OWL_DIVIDER_HW(CMU_UART0CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
289 OWL_DIVIDER_HW(CMU_UART1CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
295 OWL_DIVIDER_HW(CMU_UART2CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
301 OWL_DIVIDER_HW(CMU_UART3CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
307 OWL_DIVIDER_HW(CMU_UART4CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
313 OWL_DIVIDER_HW(CMU_UART5CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
319 OWL_DIVIDER_HW(CMU_UART6CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
325 OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
331 OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
337 OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
343 OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
349 OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
355 OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
373 OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
379 OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, hdmia_div_table),
385 OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, hdmia_div_table),
396 OWL_DIVIDER_HW(CMU_SENSORCLK, 5, 2, 0, NULL),
405 OWL_DIVIDER_HW(CMU_SSTSCLK, 20, 10, 0, NULL),