Lines Matching refs:OWL_DIVIDER_HW
208 OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL),
230 OWL_DIVIDER_HW(CMU_BISPCLK, 0, 4, 0, std12rate_div_table),
236 OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, std12rate_div_table),
242 OWL_DIVIDER_HW(CMU_SENSORCLK, 8, 4, 0, std12rate_div_table),
266 OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
272 OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
278 OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
284 OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
290 OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
296 OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
323 OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
329 OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
335 OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
341 OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
347 OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
353 OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
359 OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
365 OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table),
371 OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table),
377 OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, i2s_div_table),
383 OWL_DIVIDER_HW(CMU_AUDIOPLL, 28, 4, 0, i2s_div_table),
389 OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, nand_div_table),
395 OWL_DIVIDER_HW(CMU_NANDCCLK, 4, 3, 0, nand_div_table),