Lines Matching defs:channel
239 #define CHA 0x00 /* channel A offset */
240 #define CHB 0x40 /* channel B offset */
336 static void irq_disable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
338 if (channel == CHA) {
346 static void irq_enable(MGSLPC_INFO *info, unsigned char channel, unsigned short mask)
348 if (channel == CHA) {
686 static bool wait_command_complete(MGSLPC_INFO *info, unsigned char channel)
690 while (read_reg(info, (unsigned char)(channel+STAR)) & BIT2) {
698 static void issue_command(MGSLPC_INFO *info, unsigned char channel, unsigned char cmd)
700 wait_command_complete(info, channel);
701 write_reg(info, (unsigned char) (channel + CMDR), cmd);
2869 static void mgslpc_set_rate(MGSLPC_INFO *info, unsigned char channel, unsigned int rate)
2895 write_reg(info, (unsigned char) (channel + BGR),
2897 val = read_reg(info, (unsigned char) (channel + CCR2)) & 0x3f;
2899 write_reg(info, (unsigned char) (channel + CCR2), val);
2923 /* channel B RTS is used to enable AUXCLK driver on SP505 */
3440 /* CCR2 (channel A)