Lines Matching defs:val
59 int val;
66 val = readl_poll_timeout(trng->mem + EXYNOS_TRNG_FIFO_CTRL, val,
67 val == 0, 200, 1000000);
68 if (val < 0)
69 return val;
80 u32 val;
88 val = sss_rate / (EXYNOS_TRNG_CLOCK_RATE * 2);
89 if (val > 0x7fff) {
90 dev_err(trng->dev, "clock divider too large: %d", val);
93 val = val << 1;
94 writel_relaxed(val, trng->mem + EXYNOS_TRNG_CLKDIV);
97 val = EXYNOS_TRNG_CTRL_RNGEN;
98 writel_relaxed(val, trng->mem + EXYNOS_TRNG_CTRL);