Lines Matching refs:drvdata
77 static inline void cc_iowrite(struct cctrng_drvdata *drvdata, u32 reg, u32 val)
79 iowrite32(val, (drvdata->cc_base + reg));
81 static inline u32 cc_ioread(struct cctrng_drvdata *drvdata, u32 reg)
83 return ioread32(drvdata->cc_base + reg);
107 static int cc_trng_pm_init(struct cctrng_drvdata *drvdata)
109 struct device *dev = &(drvdata->pdev->dev);
118 static void cc_trng_pm_go(struct cctrng_drvdata *drvdata)
120 struct device *dev = &(drvdata->pdev->dev);
126 static void cc_trng_pm_fini(struct cctrng_drvdata *drvdata)
128 struct device *dev = &(drvdata->pdev->dev);
134 static inline int cc_trng_parse_sampling_ratio(struct cctrng_drvdata *drvdata)
136 struct device *dev = &(drvdata->pdev->dev);
137 struct device_node *np = drvdata->pdev->dev.of_node;
144 drvdata->smpl_ratio,
154 i, drvdata->smpl_ratio[i]);
156 if (drvdata->smpl_ratio[i] > 0)
163 static int cc_trng_change_rosc(struct cctrng_drvdata *drvdata)
165 struct device *dev = &(drvdata->pdev->dev);
167 dev_dbg(dev, "cctrng change rosc (was %d)\n", drvdata->active_rosc);
168 drvdata->active_rosc += 1;
170 while (drvdata->active_rosc < CC_TRNG_NUM_OF_ROSCS) {
171 if (drvdata->smpl_ratio[drvdata->active_rosc] > 0)
174 drvdata->active_rosc += 1;
180 static void cc_trng_enable_rnd_source(struct cctrng_drvdata *drvdata)
185 max_cycles = CCTRNG_TIMEOUT(drvdata->smpl_ratio[drvdata->active_rosc]);
186 cc_iowrite(drvdata, CC_RNG_WATCHDOG_VAL_REG_OFFSET, max_cycles);
189 cc_iowrite(drvdata, CC_RND_SOURCE_ENABLE_REG_OFFSET, 0x1);
192 cc_iowrite(drvdata, CC_RNG_IMR_REG_OFFSET, (u32)~CC_RNG_INT_MASK);
203 static inline size_t circ_buf_space(struct cctrng_drvdata *drvdata)
205 return CIRC_SPACE(drvdata->circ.head,
206 drvdata->circ.tail, CCTRNG_DATA_BUF_WORDS);
214 struct cctrng_drvdata *drvdata = (struct cctrng_drvdata *)rng->priv;
215 struct device *dev = &(drvdata->pdev->dev);
216 u32 *buf = (u32 *)drvdata->circ.buf;
222 if (!spin_trylock(&drvdata->read_lock)) {
229 cnt_w = CIRC_CNT_TO_END(drvdata->circ.head,
230 drvdata->circ.tail, CCTRNG_DATA_BUF_WORDS);
232 memcpy(data, &(buf[drvdata->circ.tail]), size);
234 circ_idx_inc(&drvdata->circ.tail, size);
238 cnt_w = CIRC_CNT(drvdata->circ.head,
239 drvdata->circ.tail, CCTRNG_DATA_BUF_WORDS);
241 memcpy(data, &(buf[drvdata->circ.tail]), size);
243 circ_idx_inc(&drvdata->circ.tail, size);
246 spin_unlock(&drvdata->read_lock);
248 if (circ_buf_space(drvdata) >= CC_TRNG_EHR_IN_WORDS) {
249 if (atomic_cmpxchg(&drvdata->pending_hw, 0, 1) == 0) {
251 if (circ_buf_space(drvdata) >= CC_TRNG_EHR_IN_WORDS) {
265 schedule_work(&drvdata->startwork);
267 atomic_set(&drvdata->pending_hw, 0);
275 static void cc_trng_hw_trigger(struct cctrng_drvdata *drvdata)
278 struct device *dev = &(drvdata->pdev->dev);
283 cc_iowrite(drvdata, CC_RNG_CLK_ENABLE_REG_OFFSET, 0x1);
286 cc_iowrite(drvdata, CC_RNG_SW_RESET_REG_OFFSET, 0x1);
292 cc_iowrite(drvdata, CC_RNG_CLK_ENABLE_REG_OFFSET, 0x1);
295 cc_iowrite(drvdata, CC_SAMPLE_CNT1_REG_OFFSET,
296 drvdata->smpl_ratio[drvdata->active_rosc]);
299 tmp_smpl_cnt = cc_ioread(drvdata, CC_SAMPLE_CNT1_REG_OFFSET);
301 } while (tmp_smpl_cnt != drvdata->smpl_ratio[drvdata->active_rosc]);
304 cc_iowrite(drvdata, CC_RND_SOURCE_ENABLE_REG_OFFSET, 0);
306 cc_iowrite(drvdata, CC_RNG_ICR_REG_OFFSET, 0xFFFFFFFF);
308 cc_iowrite(drvdata, CC_TRNG_CONFIG_REG_OFFSET, drvdata->active_rosc);
311 cc_iowrite(drvdata, CC_TRNG_DEBUG_CONTROL_REG_OFFSET, 0);
313 cc_trng_enable_rnd_source(drvdata);
320 struct cctrng_drvdata *drvdata =
322 struct device *dev = &(drvdata->pdev->dev);
326 cc_iowrite(drvdata, CC_RNG_DMA_ENABLE_REG_OFFSET, 0);
327 cc_iowrite(drvdata, CC_RND_SOURCE_ENABLE_REG_OFFSET, 0);
330 isr = cc_ioread(drvdata, CC_RNG_ISR_REG_OFFSET);
341 cc_iowrite(drvdata, CC_RNG_ICR_REG_OFFSET, isr);
358 u32 *buf = (u32 *)drvdata->circ.buf;
360 buf[drvdata->circ.head] = cc_ioread(drvdata,
366 if (buf[drvdata->circ.head] == 0) {
368 drvdata->active_rosc);
372 circ_idx_inc(&drvdata->circ.head, 1<<2);
375 atomic_set(&drvdata->pending_hw, 0);
378 if (circ_buf_space(drvdata) >= CC_TRNG_EHR_IN_WORDS) {
379 if (atomic_cmpxchg(&drvdata->pending_hw, 0, 1) == 0) {
381 cc_trng_enable_rnd_source(drvdata);
392 if ((circ_buf_space(drvdata) >= CC_TRNG_EHR_IN_WORDS) &&
393 (cc_trng_change_rosc(drvdata) == 0)) {
395 cc_trng_hw_trigger(drvdata);
397 atomic_set(&drvdata->pending_hw, 0);
404 struct cctrng_drvdata *drvdata = (struct cctrng_drvdata *)dev_id;
405 struct device *dev = &(drvdata->pdev->dev);
413 irr = cc_ioread(drvdata, CC_HOST_RGF_IRR_REG_OFFSET);
420 cc_iowrite(drvdata, CC_HOST_RGF_ICR_REG_OFFSET, irr);
425 cc_iowrite(drvdata, CC_RNG_IMR_REG_OFFSET, 0xFFFFFFFF);
430 cc_iowrite(drvdata, CC_HOST_RGF_ICR_REG_OFFSET,
436 schedule_work(&drvdata->compwork);
451 struct cctrng_drvdata *drvdata =
454 drvdata->active_rosc = 0;
455 cc_trng_hw_trigger(drvdata);
459 static int cc_trng_clk_init(struct cctrng_drvdata *drvdata)
462 struct device *dev = &(drvdata->pdev->dev);
470 drvdata->clk = clk;
472 rc = clk_prepare_enable(drvdata->clk);
481 static void cc_trng_clk_fini(struct cctrng_drvdata *drvdata)
483 clk_disable_unprepare(drvdata->clk);
490 struct cctrng_drvdata *drvdata;
496 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
497 if (!drvdata)
500 drvdata->rng.name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
501 if (!drvdata->rng.name)
504 drvdata->rng.read = cctrng_read;
505 drvdata->rng.priv = (unsigned long)drvdata;
506 drvdata->rng.quality = CC_TRNG_QUALITY;
508 platform_set_drvdata(pdev, drvdata);
509 drvdata->pdev = pdev;
511 drvdata->circ.buf = (char *)drvdata->data_buf;
517 drvdata->cc_base = devm_ioremap_resource(dev, req_mem_cc_regs);
518 if (IS_ERR(drvdata->cc_base)) {
520 return PTR_ERR(drvdata->cc_base);
526 &req_mem_cc_regs->start, drvdata->cc_base);
536 rc = cc_trng_parse_sampling_ratio(drvdata);
542 rc = cc_trng_clk_init(drvdata);
548 INIT_WORK(&drvdata->compwork, cc_trng_compwork_handler);
549 INIT_WORK(&drvdata->startwork, cc_trng_startwork_handler);
550 spin_lock_init(&drvdata->read_lock);
553 rc = devm_request_irq(dev, irq, cc_isr, IRQF_SHARED, "cctrng", drvdata);
561 val = cc_ioread(drvdata, CC_HOST_RGF_IRR_REG_OFFSET);
563 cc_iowrite(drvdata, CC_HOST_RGF_ICR_REG_OFFSET, val);
566 cc_iowrite(drvdata, CC_HOST_RGF_IMR_REG_OFFSET,
567 cc_ioread(drvdata, CC_HOST_RGF_IMR_REG_OFFSET) &
571 rc = cc_trng_pm_init(drvdata);
585 atomic_set(&drvdata->pending_hw, 1);
588 rc = hwrng_register(&drvdata->rng);
595 drvdata->active_rosc = 0;
596 cc_trng_hw_trigger(drvdata);
599 cc_trng_pm_go(drvdata);
606 cc_trng_pm_fini(drvdata);
609 cc_trng_clk_fini(drvdata);
616 struct cctrng_drvdata *drvdata = platform_get_drvdata(pdev);
621 hwrng_unregister(&drvdata->rng);
623 cc_trng_pm_fini(drvdata);
625 cc_trng_clk_fini(drvdata);
634 struct cctrng_drvdata *drvdata = dev_get_drvdata(dev);
637 cc_iowrite(drvdata, CC_HOST_POWER_DOWN_EN_REG_OFFSET,
640 clk_disable_unprepare(drvdata->clk);
645 static bool cctrng_wait_for_reset_completion(struct cctrng_drvdata *drvdata)
654 val = cc_ioread(drvdata, CC_NVM_IS_IDLE_REG_OFFSET);
668 struct cctrng_drvdata *drvdata = dev_get_drvdata(dev);
673 rc = clk_prepare_enable(drvdata->clk);
680 if (!cctrng_wait_for_reset_completion(drvdata)) {
686 cc_iowrite(drvdata, CC_HOST_RGF_IMR_REG_OFFSET,
687 cc_ioread(drvdata, CC_HOST_RGF_IMR_REG_OFFSET) &
690 cc_iowrite(drvdata, CC_HOST_POWER_DOWN_EN_REG_OFFSET,