Lines Matching defs:serverworks_private
46 } serverworks_private;
79 tables = serverworks_private.gatt_pages;
80 for (i = 0; i < serverworks_private.num_tables; i++) {
114 serverworks_private.num_tables = nr_tables;
115 serverworks_private.gatt_pages = tables;
122 #define SVRWRKS_GET_GATT(addr) (serverworks_private.gatt_pages[\
151 retval = serverworks_create_page_map(&serverworks_private.scratch_dir);
158 writel(agp_bridge->scratch_page, serverworks_private.scratch_dir.remapped+i);
159 writel(virt_to_phys(serverworks_private.scratch_dir.real) | 1, page_dir.remapped+i);
165 serverworks_free_page_map(&serverworks_private.scratch_dir);
178 pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
183 writel(virt_to_phys(serverworks_private.gatt_pages[i]->real)|1, page_dir.remapped+i);
197 serverworks_free_page_map(&serverworks_private.scratch_dir);
209 pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
210 pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,
212 pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2);
213 pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp);
240 writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH);
242 while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) {
245 dev_err(&serverworks_private.svrwrks_dev->dev,
251 writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH);
253 while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) {
256 dev_err(&serverworks_private.svrwrks_dev->dev,
273 pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);
275 serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
276 if (!serverworks_private.registers) {
281 writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE);
282 readb(serverworks_private.registers+SVWRKS_GART_CACHE); /* PCI Posting. */
284 writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE);
285 readl(serverworks_private.registers+SVWRKS_GATTBASE); /* PCI Posting. */
287 cap_reg = readw(serverworks_private.registers+SVWRKS_COMMAND);
290 writew(cap_reg, serverworks_private.registers+SVWRKS_COMMAND);
291 readw(serverworks_private.registers+SVWRKS_COMMAND);
293 pci_read_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, &enable_reg);
295 pci_write_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, enable_reg);
298 agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
301 pci_read_config_dword(serverworks_private.svrwrks_dev,
317 iounmap((void __iomem *) serverworks_private.registers);
405 pci_read_config_dword(serverworks_private.svrwrks_dev,
416 pci_write_config_dword(serverworks_private.svrwrks_dev,
485 serverworks_private.svrwrks_dev = bridge_dev;
486 serverworks_private.gart_addr_ofs = 0x10;
496 serverworks_private.mm_addr_ofs = 0x18;
498 serverworks_private.mm_addr_ofs = 0x14;
500 pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs, &temp);
503 serverworks_private.mm_addr_ofs + 4, &temp2);
516 bridge->dev_private_data = &serverworks_private;
530 pci_dev_put(serverworks_private.svrwrks_dev);
531 serverworks_private.svrwrks_dev = NULL;