Lines Matching defs:intel_private
89 } intel_private;
91 #define INTEL_GTT_GEN intel_private.driver->gen
92 #define IS_G33 intel_private.driver->is_g33
93 #define IS_PINEVIEW intel_private.driver->is_pineview
94 #define IS_IRONLAKE intel_private.driver->is_ironlake
95 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
113 if (!pci_map_sg(intel_private.pcidev,
129 pci_unmap_sg(intel_private.pcidev, sg_list,
182 intel_private.i81x_gtt_table = gtt_table;
184 reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
186 intel_private.registers = ioremap(reg_addr, KB(64));
187 if (!intel_private.registers)
191 intel_private.registers+I810_PGETBL_CTL);
193 intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
195 if ((readl(intel_private.registers+I810_DRAM_CTL)
197 dev_info(&intel_private.pcidev->dev,
199 intel_private.num_dcache_entries = 1024;
207 writel(0, intel_private.registers+I810_PGETBL_CTL);
208 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
218 > intel_private.num_dcache_entries)
226 intel_private.driver->write_entry(addr,
304 if (intel_private.needs_dmar) {
305 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
307 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) {
312 intel_private.scratch_page_dma = dma_addr;
314 intel_private.scratch_page_dma = page_to_phys(page);
316 intel_private.scratch_page = page;
335 writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
349 pci_read_config_word(intel_private.bridge_dev,
352 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
353 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
365 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
422 dev_info(&intel_private.bridge_dev->dev, "detected %lluK %s memory\n",
425 dev_info(&intel_private.bridge_dev->dev,
438 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
440 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
443 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
446 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
455 pci_read_config_word(intel_private.bridge_dev,
474 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
497 dev_info(&intel_private.pcidev->dev,
513 return intel_private.gtt_mappable_entries;
524 pci_read_config_dword(intel_private.bridge_dev,
535 pci_read_config_word(intel_private.bridge_dev,
544 aperture_size = pci_resource_len(intel_private.pcidev, 2);
552 set_pages_wb(intel_private.scratch_page, 1);
553 if (intel_private.needs_dmar)
554 pci_unmap_page(intel_private.pcidev,
555 intel_private.scratch_page_dma,
557 __free_page(intel_private.scratch_page);
562 intel_private.driver->cleanup();
564 iounmap(intel_private.gtt);
565 iounmap(intel_private.registers);
576 const unsigned short gpu_devid = intel_private.pcidev->device;
609 ret = intel_private.driver->setup();
613 intel_private.gtt_mappable_entries = intel_gtt_mappable_entries();
614 intel_private.gtt_total_entries = intel_gtt_total_entries();
617 intel_private.PGETBL_save =
618 readl(intel_private.registers+I810_PGETBL_CTL)
622 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
624 dev_info(&intel_private.bridge_dev->dev,
626 intel_private.gtt_total_entries * 4,
627 intel_private.gtt_mappable_entries * 4);
629 gtt_map_size = intel_private.gtt_total_entries * 4;
631 intel_private.gtt = NULL;
633 intel_private.gtt = ioremap_wc(intel_private.gtt_phys_addr,
635 if (intel_private.gtt == NULL)
636 intel_private.gtt = ioremap(intel_private.gtt_phys_addr,
638 if (intel_private.gtt == NULL) {
639 intel_private.driver->cleanup();
640 iounmap(intel_private.registers);
648 intel_private.stolen_size = intel_gtt_stolen_size();
650 intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2;
663 intel_private.gma_bus_addr = pci_bus_address(intel_private.pcidev, bar);
682 aper_size = (intel_private.gtt_mappable_entries << PAGE_SHIFT) / MB(1);
724 writel(readl(intel_private.registers+I830_HIC) | (1<<31),
725 intel_private.registers+I830_HIC);
727 while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
743 writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
753 pci_read_config_word(intel_private.bridge_dev,
756 pci_write_config_word(intel_private.bridge_dev,
759 pci_read_config_word(intel_private.bridge_dev,
762 dev_err(&intel_private.pcidev->dev,
773 writel(0, intel_private.registers+GFX_FLSH_CNTL);
775 reg = intel_private.registers+I810_PGETBL_CTL;
776 writel(intel_private.PGETBL_save, reg);
778 dev_err(&intel_private.pcidev->dev,
780 readl(reg), intel_private.PGETBL_save);
785 writel(0, intel_private.registers+GFX_FLSH_CNTL);
795 reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
797 intel_private.registers = ioremap(reg_addr, KB(64));
798 if (!intel_private.registers)
801 intel_private.gtt_phys_addr = reg_addr + I810_PTE_BASE;
826 intel_private.clear_fake_agp = true;
827 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
850 intel_private.driver->write_entry(addr, pg, flags);
851 readl(intel_private.gtt + pg);
852 if (intel_private.driver->chipset_flush)
853 intel_private.driver->chipset_flush();
873 intel_private.driver->write_entry(addr, j, flags);
877 readl(intel_private.gtt + j - 1);
878 if (intel_private.driver->chipset_flush)
879 intel_private.driver->chipset_flush();
893 intel_private.driver->write_entry(addr,
904 if (intel_private.clear_fake_agp) {
905 int start = intel_private.stolen_size / PAGE_SIZE;
906 int end = intel_private.gtt_mappable_entries;
908 intel_private.clear_fake_agp = false;
917 if (pg_start + mem->page_count > intel_private.gtt_total_entries)
923 if (!intel_private.driver->check_flags(type))
929 if (intel_private.needs_dmar) {
956 intel_private.driver->write_entry(intel_private.scratch_page_dma,
972 if (intel_private.needs_dmar) {
987 if (pg_count != intel_private.num_dcache_entries)
1010 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1012 pcibios_align_resource, intel_private.bridge_dev);
1022 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1025 intel_private.resource_valid = 1;
1026 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1030 intel_private.resource_valid = 1;
1031 intel_private.ifp_resource.start = temp;
1032 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1033 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1036 intel_private.resource_valid = 0;
1045 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1046 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1052 intel_private.resource_valid = 1;
1053 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1054 upper_32_bits(intel_private.ifp_resource.start));
1055 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1062 intel_private.resource_valid = 1;
1063 intel_private.ifp_resource.start = l64;
1064 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1065 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1068 intel_private.resource_valid = 0;
1075 if (intel_private.ifp_resource.start)
1082 intel_private.ifp_resource.name = "Intel Flush Page";
1083 intel_private.ifp_resource.flags = IORESOURCE_MEM;
1092 if (intel_private.ifp_resource.start)
1093 intel_private.i9xx_flush_page = ioremap(intel_private.ifp_resource.start, PAGE_SIZE);
1094 if (!intel_private.i9xx_flush_page)
1095 dev_err(&intel_private.pcidev->dev,
1101 if (intel_private.i9xx_flush_page)
1102 iounmap(intel_private.i9xx_flush_page);
1103 if (intel_private.resource_valid)
1104 release_resource(&intel_private.ifp_resource);
1105 intel_private.ifp_resource.start = 0;
1106 intel_private.resource_valid = 0;
1112 if (intel_private.i9xx_flush_page)
1113 writel(1, intel_private.i9xx_flush_page);
1128 writel_relaxed(addr | pte_flags, intel_private.gtt + entry);
1136 reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR);
1138 intel_private.registers = ioremap(reg_addr, size);
1139 if (!intel_private.registers)
1144 intel_private.gtt_phys_addr =
1145 pci_resource_start(intel_private.pcidev, I915_PTE_BAR);
1148 intel_private.gtt_phys_addr = reg_addr + MB(2);
1151 intel_private.gtt_phys_addr = reg_addr + KB(512);
1359 intel_private.pcidev = gmch_device;
1372 intel_private.pcidev = pci_dev_get(gpu_pdev);
1373 intel_private.driver =
1379 intel_private.driver =
1385 if (!intel_private.driver)
1394 bridge->dev_private_data = &intel_private;
1405 if (intel_private.refcount++)
1408 intel_private.bridge_dev = pci_dev_get(bridge_pdev);
1413 mask = intel_private.driver->dma_mask_size;
1414 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1415 dev_err(&intel_private.pcidev->dev,
1419 pci_set_consistent_dma_mask(intel_private.pcidev,
1437 *gtt_total = intel_private.gtt_total_entries << PAGE_SHIFT;
1438 *mappable_base = intel_private.gma_bus_addr;
1439 *mappable_end = intel_private.gtt_mappable_entries << PAGE_SHIFT;
1445 if (intel_private.driver->chipset_flush)
1446 intel_private.driver->chipset_flush();
1452 if (--intel_private.refcount)
1455 if (intel_private.scratch_page)
1457 if (intel_private.pcidev)
1458 pci_dev_put(intel_private.pcidev);
1459 if (intel_private.bridge_dev)
1460 pci_dev_put(intel_private.bridge_dev);
1461 intel_private.driver = NULL;