Lines Matching defs:mhi_cntrl
22 void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl,
27 void __iomem *base = mhi_cntrl->bhie;
28 struct device *dev = &mhi_cntrl->mhi_dev->dev;
39 mhi_write_reg(mhi_cntrl, base, BHIE_RXVECADDR_HIGH_OFFS,
42 mhi_write_reg(mhi_cntrl, base, BHIE_RXVECADDR_LOW_OFFS,
45 mhi_write_reg(mhi_cntrl, base, BHIE_RXVECSIZE_OFFS, mhi_buf->len);
48 mhi_write_reg_field(mhi_cntrl, base, BHIE_RXVECDB_OFFS,
57 static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl)
63 u32 retry = (mhi_cntrl->timeout_ms * 1000) / delayus;
66 void __iomem *base = mhi_cntrl->bhie;
67 struct device *dev = &mhi_cntrl->mhi_dev->dev;
70 to_mhi_pm_state_str(mhi_cntrl->pm_state),
71 TO_MHI_STATE_STR(mhi_cntrl->dev_state),
72 TO_MHI_EXEC_STR(mhi_cntrl->ee));
84 mhi_cntrl->pm_state = MHI_PM_LD_ERR_FATAL_DETECT;
94 ee = mhi_get_exec_env(mhi_cntrl);
97 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_SYS_ERR);
101 ee = mhi_get_exec_env(mhi_cntrl);
112 mhi_write_reg(mhi_cntrl, mhi_cntrl->regs,
118 ee = mhi_get_exec_env(mhi_cntrl);
126 ret = mhi_read_reg_field(mhi_cntrl, base, BHIE_RXVECSTATUS_OFFS,
139 ee = mhi_get_exec_env(mhi_cntrl);
140 ret = mhi_read_reg(mhi_cntrl, base, BHIE_RXVECSTATUS_OFFS, &rx_status);
150 int mhi_download_rddm_img(struct mhi_controller *mhi_cntrl, bool in_panic)
152 void __iomem *base = mhi_cntrl->bhie;
153 struct device *dev = &mhi_cntrl->mhi_dev->dev;
157 return __mhi_download_rddm_in_panic(mhi_cntrl);
162 wait_event_timeout(mhi_cntrl->state_event,
163 mhi_read_reg_field(mhi_cntrl, base,
168 msecs_to_jiffies(mhi_cntrl->timeout_ms));
174 static int mhi_fw_load_amss(struct mhi_controller *mhi_cntrl,
177 void __iomem *base = mhi_cntrl->bhie;
178 struct device *dev = &mhi_cntrl->mhi_dev->dev;
179 rwlock_t *pm_lock = &mhi_cntrl->pm_lock;
184 if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) {
192 mhi_write_reg(mhi_cntrl, base, BHIE_TXVECADDR_HIGH_OFFS,
195 mhi_write_reg(mhi_cntrl, base, BHIE_TXVECADDR_LOW_OFFS,
198 mhi_write_reg(mhi_cntrl, base, BHIE_TXVECSIZE_OFFS, mhi_buf->len);
200 mhi_write_reg_field(mhi_cntrl, base, BHIE_TXVECDB_OFFS,
206 ret = wait_event_timeout(mhi_cntrl->state_event,
207 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state) ||
208 mhi_read_reg_field(mhi_cntrl, base,
213 msecs_to_jiffies(mhi_cntrl->timeout_ms));
214 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state) ||
221 static int mhi_fw_load_sbl(struct mhi_controller *mhi_cntrl,
227 void __iomem *base = mhi_cntrl->bhi;
228 rwlock_t *pm_lock = &mhi_cntrl->pm_lock;
229 struct device *dev = &mhi_cntrl->mhi_dev->dev;
242 if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) {
250 mhi_write_reg(mhi_cntrl, base, BHI_STATUS, 0);
251 mhi_write_reg(mhi_cntrl, base, BHI_IMGADDR_HIGH,
253 mhi_write_reg(mhi_cntrl, base, BHI_IMGADDR_LOW,
255 mhi_write_reg(mhi_cntrl, base, BHI_IMGSIZE, size);
256 mhi_write_reg(mhi_cntrl, base, BHI_IMGTXDB, session_id);
260 ret = wait_event_timeout(mhi_cntrl->state_event,
261 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state) ||
262 mhi_read_reg_field(mhi_cntrl, base, BHI_STATUS,
265 msecs_to_jiffies(mhi_cntrl->timeout_ms));
266 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))
272 if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) {
274 ret = mhi_read_reg(mhi_cntrl, base,
293 void mhi_free_bhie_table(struct mhi_controller *mhi_cntrl,
300 mhi_free_coherent(mhi_cntrl, mhi_buf->len, mhi_buf->buf,
307 int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl,
311 size_t seg_size = mhi_cntrl->seg_len;
337 mhi_buf->buf = mhi_alloc_coherent(mhi_cntrl, vec_size,
352 mhi_free_coherent(mhi_cntrl, mhi_buf->len, mhi_buf->buf,
361 static void mhi_firmware_copy(struct mhi_controller *mhi_cntrl,
386 void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl)
390 struct device *dev = &mhi_cntrl->mhi_dev->dev;
397 if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
403 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_SERIALNU,
404 &mhi_cntrl->serial_number);
408 for (i = 0; i < ARRAY_SIZE(mhi_cntrl->oem_pk_hash); i++) {
409 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_OEMPKHASH(i),
410 &mhi_cntrl->oem_pk_hash[i]);
418 if (mhi_cntrl->ee == MHI_EE_PTHRU)
421 fw_name = (mhi_cntrl->ee == MHI_EE_EDL) ?
422 mhi_cntrl->edl_image : mhi_cntrl->fw_image;
424 if (!fw_name || (mhi_cntrl->fbc_download && (!mhi_cntrl->sbl_size ||
425 !mhi_cntrl->seg_len))) {
437 size = (mhi_cntrl->fbc_download) ? mhi_cntrl->sbl_size : firmware->size;
443 buf = mhi_alloc_coherent(mhi_cntrl, size, &dma_addr, GFP_KERNEL);
451 ret = mhi_fw_load_sbl(mhi_cntrl, dma_addr, size);
452 mhi_free_coherent(mhi_cntrl, size, buf, dma_addr);
454 if (!mhi_cntrl->fbc_download || ret || mhi_cntrl->ee == MHI_EE_EDL)
463 if (mhi_cntrl->ee == MHI_EE_EDL)
466 write_lock_irq(&mhi_cntrl->pm_lock);
467 mhi_cntrl->dev_state = MHI_STATE_RESET;
468 write_unlock_irq(&mhi_cntrl->pm_lock);
474 if (mhi_cntrl->fbc_download) {
475 ret = mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->fbc_image,
481 mhi_firmware_copy(mhi_cntrl, firmware, mhi_cntrl->fbc_image);
486 ret = mhi_ready_state_transition(mhi_cntrl);
488 if (!mhi_cntrl->fbc_download)
497 ret = wait_event_timeout(mhi_cntrl->state_event,
498 mhi_cntrl->ee == MHI_EE_SBL ||
499 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
500 msecs_to_jiffies(mhi_cntrl->timeout_ms));
502 if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
508 image_info = mhi_cntrl->fbc_image;
509 ret = mhi_fw_load_amss(mhi_cntrl,
520 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image);
521 mhi_cntrl->fbc_image = NULL;