Lines Matching defs:val
284 u32 val = readl(skdev->mem_map[1] + offset);
287 dev_dbg(&skdev->pdev->dev, "offset %x = %x\n", offset, val);
288 return val;
291 static inline void skd_reg_write32(struct skd_device *skdev, u32 val,
294 writel(val, skdev->mem_map[1] + offset);
296 dev_dbg(&skdev->pdev->dev, "offset %x = %x\n", offset, val);
299 static inline void skd_reg_write64(struct skd_device *skdev, u64 val,
302 writeq(val, skdev->mem_map[1] + offset);
305 val);
2033 u32 val;
2036 val = FIT_ISH_FW_STATE_CHANGE +
2041 SKD_WRITEL(skdev, ~val, FIT_INT_MASK_HOST);
2042 dev_dbg(&skdev->pdev->dev, "interrupt mask=0x%x\n", ~val);
2044 val = SKD_READL(skdev, FIT_CONTROL);
2045 val |= FIT_CR_ENABLE_INTERRUPTS;
2046 dev_dbg(&skdev->pdev->dev, "control=0x%x\n", val);
2047 SKD_WRITEL(skdev, val, FIT_CONTROL);
2058 u32 val;
2060 val = SKD_READL(skdev, FIT_CONTROL);
2061 val |= (FIT_CR_SOFT_RESET);
2062 dev_dbg(&skdev->pdev->dev, "control=0x%x\n", val);
2063 SKD_WRITEL(skdev, val, FIT_CONTROL);