Lines Matching refs:port
214 * @port Pointer to the port structure.
220 static inline void mtip_issue_ncq_command(struct mtip_port *port, int tag)
225 spin_lock(&port->cmd_issue_lock[group]);
227 port->s_active[MTIP_TAG_INDEX(tag)]);
229 port->cmd_issue[MTIP_TAG_INDEX(tag)]);
230 spin_unlock(&port->cmd_issue_lock[group]);
236 * @port Pointer to the port data structure
242 static int mtip_enable_fis(struct mtip_port *port, int enable)
247 tmp = readl(port->mmio + PORT_CMD);
249 writel(tmp | PORT_CMD_FIS_RX, port->mmio + PORT_CMD);
251 writel(tmp & ~PORT_CMD_FIS_RX, port->mmio + PORT_CMD);
254 readl(port->mmio + PORT_CMD);
262 * @port Pointer to the port data structure
268 static int mtip_enable_engine(struct mtip_port *port, int enable)
273 tmp = readl(port->mmio + PORT_CMD);
275 writel(tmp | PORT_CMD_START, port->mmio + PORT_CMD);
277 writel(tmp & ~PORT_CMD_START, port->mmio + PORT_CMD);
279 readl(port->mmio + PORT_CMD);
284 * Enables the port DMA engine and FIS reception.
289 static inline void mtip_start_port(struct mtip_port *port)
292 mtip_enable_fis(port, 1);
295 mtip_enable_engine(port, 1);
299 * Deinitialize a port by disabling port interrupts, the DMA engine,
302 * @port Pointer to the port structure
307 static inline void mtip_deinit_port(struct mtip_port *port)
309 /* Disable interrupts on this port */
310 writel(0, port->mmio + PORT_IRQ_MASK);
313 mtip_enable_engine(port, 0);
316 mtip_enable_fis(port, 0);
320 * Initialize a port.
322 * This function deinitializes the port by calling mtip_deinit_port() and
324 * clearing the SError register and any pending port interrupts before
325 * re-enabling the default set of port interrupts.
327 * @port Pointer to the port structure.
332 static void mtip_init_port(struct mtip_port *port)
335 mtip_deinit_port(port);
338 if (readl(port->dd->mmio + HOST_CAP) & HOST_CAP_64) {
339 writel((port->command_list_dma >> 16) >> 16,
340 port->mmio + PORT_LST_ADDR_HI);
341 writel((port->rxfis_dma >> 16) >> 16,
342 port->mmio + PORT_FIS_ADDR_HI);
343 set_bit(MTIP_PF_HOST_CAP_64, &port->flags);
346 writel(port->command_list_dma & 0xFFFFFFFF,
347 port->mmio + PORT_LST_ADDR);
348 writel(port->rxfis_dma & 0xFFFFFFFF, port->mmio + PORT_FIS_ADDR);
351 writel(readl(port->mmio + PORT_SCR_ERR), port->mmio + PORT_SCR_ERR);
354 for (i = 0; i < port->dd->slot_groups; i++)
355 writel(0xFFFFFFFF, port->completed[i]);
357 /* Clear any pending interrupts for this port */
358 writel(readl(port->mmio + PORT_IRQ_STAT), port->mmio + PORT_IRQ_STAT);
361 writel(readl(port->dd->mmio + HOST_IRQ_STAT),
362 port->dd->mmio + HOST_IRQ_STAT);
364 /* Enable port interrupts */
365 writel(DEF_PORT_IRQ, port->mmio + PORT_IRQ_MASK);
369 * Restart a port
371 * @port Pointer to the port data structure.
376 static void mtip_restart_port(struct mtip_port *port)
381 mtip_enable_engine(port, 0);
385 while ((readl(port->mmio + PORT_CMD) & PORT_CMD_LIST_ON)
389 if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &port->dd->dd_flag))
396 if (readl(port->mmio + PORT_CMD) & PORT_CMD_LIST_ON) {
397 dev_warn(&port->dd->pdev->dev,
400 if (mtip_hba_reset(port->dd))
401 dev_err(&port->dd->pdev->dev,
408 dev_warn(&port->dd->pdev->dev, "Issuing COM reset\n");
411 writel(readl(port->mmio + PORT_SCR_CTL) |
412 1, port->mmio + PORT_SCR_CTL);
413 readl(port->mmio + PORT_SCR_CTL);
420 if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &port->dd->dd_flag))
424 writel(readl(port->mmio + PORT_SCR_CTL) & ~1,
425 port->mmio + PORT_SCR_CTL);
426 readl(port->mmio + PORT_SCR_CTL);
430 while (((readl(port->mmio + PORT_SCR_STAT) & 0x01) == 0)
434 if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &port->dd->dd_flag))
437 if ((readl(port->mmio + PORT_SCR_STAT) & 0x01) == 0)
438 dev_warn(&port->dd->pdev->dev,
441 mtip_init_port(port);
442 mtip_start_port(port);
457 mtip_init_port(dd->port);
458 mtip_start_port(dd->port);
485 static int mtip_read_log_page(struct mtip_port *port, u8 page, u16 *buffer,
487 static int mtip_get_smart_attr(struct mtip_port *port, unsigned int id,
510 struct mtip_port *port;
522 port = dd->port;
524 if (test_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags)) {
536 completed = readl(port->completed[group]);
541 writel(completed, port->completed[group]);
562 /* Restart the port */
564 mtip_restart_port(port);
567 rv = mtip_read_log_page(dd->port, ATA_LOG_SATA_NCQ,
568 dd->port->log_buf,
569 dd->port->log_buf_dma, 1);
575 buf = (unsigned char *)dd->port->log_buf;
640 mtip_issue_ncq_command(port, tag);
646 dev_warn(&port->dd->pdev->dev,
658 static inline void mtip_workq_sdbfx(struct mtip_port *port, int group,
661 struct driver_data *dd = port->dd;
670 writel(completed, port->completed[group]);
697 struct mtip_port *port = dd->port;
700 if (test_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags) && cmd) {
702 int status = readl(port->cmd_issue[group]);
717 writel((1 << 26), dd->port->mmio + PORT_SCR_ERR);
723 writel((1 << 16), dd->port->mmio + PORT_SCR_ERR);
734 set_bit(MTIP_PF_EH_ACTIVE_BIT, &dd->port->flags);
735 wake_up_interruptible(&dd->port->svc_wait);
742 struct mtip_port *port = dd->port;
752 /* Acknowledge the interrupt status on the port.*/
753 port_stat = readl(port->mmio + PORT_IRQ_STAT);
758 writel(port_stat, port->mmio + PORT_IRQ_STAT);
760 /* Demux port status */
769 twork->completed = readl(port->completed[i]);
786 mtip_workq_sdbfx(port, 0,
838 static void mtip_issue_non_ncq_command(struct mtip_port *port, int tag)
840 writel(1 << MTIP_TAG_BIT(tag), port->cmd_issue[MTIP_TAG_INDEX(tag)]);
843 static bool mtip_pause_ncq(struct mtip_port *port,
848 task_file_data = readl(port->mmio+PORT_TFDATA);
853 port->ic_pause_timer = jiffies;
857 set_bit(MTIP_PF_DM_ACTIVE_BIT, &port->flags);
858 port->ic_pause_timer = jiffies;
864 clear_bit(MTIP_DDF_SEC_LOCK_BIT, &port->dd->dd_flag);
865 clear_bit(MTIP_DDF_REBUILD_FAILED_BIT, &port->dd->dd_flag);
867 mtip_restart_port(port);
868 clear_bit(MTIP_PF_SE_ACTIVE_BIT, &port->flags);
875 static bool mtip_commands_active(struct mtip_port *port)
884 active = readl(port->s_active[0]) & 0xFFFFFFFE;
885 for (n = 1; n < port->dd->slot_groups; n++)
886 active |= readl(port->s_active[n]);
892 * Wait for port to quiesce
894 * @port Pointer to port data structure
901 static int mtip_quiesce_io(struct mtip_port *port, unsigned long timeout)
906 blk_mq_quiesce_queue(port->dd->queue);
910 if (test_bit(MTIP_PF_SVC_THD_ACTIVE_BIT, &port->flags) &&
911 test_bit(MTIP_PF_ISSUE_CMDS_BIT, &port->flags)) {
918 if (mtip_check_surprise_removal(port->dd->pdev))
921 active = mtip_commands_active(port);
926 blk_mq_unquiesce_queue(port->dd->queue);
929 blk_mq_unquiesce_queue(port->dd->queue);
943 * @port Pointer to the port data structure.
958 static int mtip_exec_internal_command(struct mtip_port *port,
967 struct driver_data *dd = port->dd;
992 set_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags);
995 set_bit(MTIP_PF_SE_ACTIVE_BIT, &port->flags);
997 clear_bit(MTIP_PF_DM_ACTIVE_BIT, &port->flags);
1001 if (mtip_quiesce_io(port, MTIP_QUIESCE_IO_TIMEOUT_MS) < 0) {
1004 clear_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags);
1005 wake_up_interruptible(&port->svc_wait);
1039 if (readl(port->cmd_issue[MTIP_TAG_INDEX(MTIP_TAG_INTERNAL)])
1050 clear_bit(MTIP_PF_IC_ACTIVE_BIT, &port->flags);
1051 if (rv >= 0 && mtip_pause_ncq(port, fis)) {
1055 wake_up_interruptible(&port->svc_wait);
1091 *timeout = ((*(dd->port->identify + 90) * 2) * 60000);
1093 *timeout = ((*(dd->port->identify + 89) * 2) * 60000);
1116 * into the identify data buffer (@e port->identify) in the
1117 * port data structure.
1119 * port->identify_valid is non-zero.
1121 * @port Pointer to the port structure.
1130 static int mtip_get_identify(struct mtip_port *port, void __user *user_buffer)
1135 if (test_bit(MTIP_DDF_REMOVE_PENDING_BIT, &port->dd->dd_flag))
1145 port->identify_valid = 0;
1148 memset(port->identify, 0, sizeof(u16) * ATA_ID_WORDS);
1151 if (mtip_exec_internal_command(port,
1154 port->identify_dma,
1169 ata_swap_string(port->identify + 27, 40); /* model string*/
1170 ata_swap_string(port->identify + 23, 8); /* firmware string*/
1171 ata_swap_string(port->identify + 10, 20); /* serial# string*/
1176 port->identify[i] = le16_to_cpu(port->identify[i]);
1181 if (port->identify[128] & 0x4)
1182 set_bit(MTIP_DDF_SEC_LOCK_BIT, &port->dd->dd_flag);
1184 clear_bit(MTIP_DDF_SEC_LOCK_BIT, &port->dd->dd_flag);
1187 port->identify_valid = 1;
1192 port->identify,
1206 * @port Pointer to the port structure.
1212 static int mtip_standby_immediate(struct mtip_port *port)
1225 mtip_set_timeout(port->dd, &fis, &timeout, 0);
1228 rv = mtip_exec_internal_command(port,
1238 dev_warn(&port->dd->pdev->dev,
1247 * @port pointer to the port structure.
1256 static int mtip_read_log_page(struct mtip_port *port, u8 page, u16 *buffer,
1273 return mtip_exec_internal_command(port,
1285 * @port pointer to the port structure.
1292 static int mtip_get_smart_data(struct mtip_port *port, u8 *buffer,
1307 return mtip_exec_internal_command(port,
1319 * @port pointer to the port structure
1327 static int mtip_get_smart_attr(struct mtip_port *port, unsigned int id,
1336 if (!port->identify_valid) {
1337 dev_warn(&port->dd->pdev->dev, "IDENTIFY DATA not valid\n");
1340 if (!(port->identify[82] & 0x1)) {
1341 dev_warn(&port->dd->pdev->dev, "SMART not supported\n");
1344 if (!(port->identify[85] & 0x1)) {
1345 dev_warn(&port->dd->pdev->dev, "SMART not enabled\n");
1349 memset(port->smart_buf, 0, ATA_SECT_SIZE);
1350 rv = mtip_get_smart_data(port, port->smart_buf, port->smart_buf_dma);
1352 dev_warn(&port->dd->pdev->dev, "Failed to ge SMART data\n");
1356 pattr = (struct smart_attr *)(port->smart_buf + 2);
1364 dev_warn(&port->dd->pdev->dev,
1384 struct mtip_port *port = dd->port;
1386 raw0 = port->identify[100];
1387 raw1 = port->identify[101];
1388 raw2 = port->identify[102];
1389 raw3 = port->identify[103];
1392 return (bool) !!port->identify_valid;
1398 * @port Pointer to the port data structure.
1403 static void mtip_dump_identify(struct mtip_port *port)
1409 if (!port->identify_valid)
1412 strlcpy(cbuf, (char *)(port->identify+10), 21);
1413 dev_info(&port->dd->pdev->dev,
1416 strlcpy(cbuf, (char *)(port->identify+23), 9);
1417 dev_info(&port->dd->pdev->dev,
1420 strlcpy(cbuf, (char *)(port->identify+27), 41);
1421 dev_info(&port->dd->pdev->dev, "Model: %s\n", cbuf);
1423 dev_info(&port->dd->pdev->dev, "Security: %04x %s\n",
1424 port->identify[128],
1425 port->identify[128] & 0x4 ? "(LOCKED)" : "");
1427 if (mtip_hw_get_capacity(port->dd, §ors))
1428 dev_info(&port->dd->pdev->dev,
1433 pci_read_config_word(port->dd->pdev, PCI_REVISION_ID, &revid);
1445 dev_info(&port->dd->pdev->dev,
1488 static int exec_drive_task(struct mtip_port *port, u8 *command)
1491 struct host_to_dev_fis *reply = (port->rxfis + RX_FIS_D2H_REG);
1506 mtip_set_timeout(port->dd, &fis, &to, 0);
1519 if (mtip_exec_internal_command(port,
1547 * @param port Pointer to the port data structure.
1557 static int exec_drive_command(struct mtip_port *port, u8 *command,
1571 buf = dma_alloc_coherent(&port->dd->pdev->dev,
1576 dev_err(&port->dd->pdev->dev,
1596 mtip_set_timeout(port->dd, &fis, &to, 0);
1599 reply = (port->rxfis + RX_FIS_PIO_SETUP);
1601 reply = (port->rxfis + RX_FIS_D2H_REG);
1613 if (mtip_exec_internal_command(port,
1648 dma_free_coherent(&port->dd->pdev->dev,
1767 reply = (dd->port->rxfis + RX_FIS_PIO_SETUP);
1770 reply = (dd->port->rxfis + RX_FIS_PIO_SETUP);
1773 reply = (dd->port->rxfis + RX_FIS_D2H_REG);
1852 if (mtip_exec_internal_command(dd->port,
1863 task_file_data = readl(dd->port->mmio+PORT_TFDATA);
1866 reply = dd->port->rxfis + RX_FIS_PIO_SETUP;
1869 reply = dd->port->rxfis + RX_FIS_D2H_REG;
1960 if (copy_to_user((void __user *)arg, dd->port->identify,
1976 if (exec_drive_command(dd->port,
2000 if (exec_drive_task(dd->port, drive_command))
2062 dd->port->command_list + sizeof(struct mtip_cmd_hdr) * rq->tag;
2064 struct mtip_port *port = dd->port;
2074 prefetch(&port->flags);
2113 if (test_bit(MTIP_PF_HOST_CAP_64, &dd->port->flags))
2124 if (unlikely(port->flags & MTIP_PF_PAUSE_IO)) {
2125 set_bit(rq->tag, port->cmds_to_issue);
2126 set_bit(MTIP_PF_ISSUE_CMDS_BIT, &port->flags);
2131 mtip_issue_ncq_command(port, rq->tag);
2177 if (dd->port &&
2178 dd->port->identify &&
2179 dd->port->identify_valid) {
2181 (char *) (dd->port->identify + 10), 21);
2182 status = *(dd->port->identify + 141);
2188 if (dd->port &&
2189 test_bit(MTIP_PF_REBUILD_BIT, &dd->port->flags)) {
2207 if (dd->port &&
2208 dd->port->identify &&
2209 dd->port->identify_valid) {
2211 (char *) (dd->port->identify+10), 21);
2212 status = *(dd->port->identify + 141);
2218 if (dd->port &&
2219 test_bit(MTIP_PF_REBUILD_BIT, &dd->port->flags)) {
2290 readl(dd->port->s_active[n]));
2297 readl(dd->port->cmd_issue[n]));
2304 readl(dd->port->completed[n]));
2308 readl(dd->port->mmio + PORT_IRQ_STAT));
2318 dd->port->cmds_to_issue[n/2] >> (32*(n&1));
2320 group_allocated = dd->port->cmds_to_issue[n];
2352 size += sprintf(&buf[size], "Flag-port : [ %08lX ]\n",
2353 dd->port->flags);
2556 if (mtip_get_identify(dd->port, NULL) < 0)
2559 if (*(dd->port->identify + MTIP_FTL_REBUILD_OFFSET) ==
2595 atomic_inc(&dd->port->cmd_slot_unal);
2607 clear_bit(req->tag, dd->port->cmds_to_issue);
2617 set_bit(req->tag, dd->port->cmds_to_issue);
2636 struct mtip_port *port = dd->port;
2640 test_bit(MTIP_PF_SVC_THD_STOP_BIT, &port->flags))
2642 clear_bit(MTIP_PF_SVC_THD_ACTIVE_BIT, &port->flags);
2648 wait_event_interruptible(port->svc_wait, (port->flags) &&
2649 (port->flags & MTIP_PF_SVC_THD_WORK));
2652 test_bit(MTIP_PF_SVC_THD_STOP_BIT, &port->flags))
2659 set_bit(MTIP_PF_SVC_THD_ACTIVE_BIT, &port->flags);
2663 if (test_bit(MTIP_PF_EH_ACTIVE_BIT, &port->flags)) {
2665 clear_bit(MTIP_PF_EH_ACTIVE_BIT, &port->flags);
2668 if (test_bit(MTIP_PF_EH_ACTIVE_BIT, &port->flags))
2671 if (test_bit(MTIP_PF_TO_ACTIVE_BIT, &port->flags)) {
2687 set_bit(MTIP_PF_ISSUE_CMDS_BIT, &dd->port->flags);
2693 clear_bit(MTIP_PF_TO_ACTIVE_BIT, &dd->port->flags);
2698 if (test_bit(MTIP_PF_ISSUE_CMDS_BIT, &port->flags)) {
2704 slot = find_next_bit(port->cmds_to_issue,
2721 mtip_issue_ncq_command(port, slot);
2723 clear_bit(slot, port->cmds_to_issue);
2726 clear_bit(MTIP_PF_ISSUE_CMDS_BIT, &port->flags);
2729 if (test_bit(MTIP_PF_REBUILD_BIT, &port->flags)) {
2731 clear_bit(MTIP_PF_REBUILD_BIT, &port->flags);
2749 struct mtip_port *port = dd->port;
2751 if (port->block1)
2753 port->block1, port->block1_dma);
2755 if (port->command_list) {
2757 port->command_list, port->command_list_dma);
2771 struct mtip_port *port = dd->port;
2774 port->block1 =
2776 &port->block1_dma, GFP_KERNEL);
2777 if (!port->block1)
2781 port->command_list =
2783 &port->command_list_dma, GFP_KERNEL);
2784 if (!port->command_list) {
2786 port->block1, port->block1_dma);
2787 port->block1 = NULL;
2788 port->block1_dma = 0;
2793 port->rxfis = port->block1 + AHCI_RX_FIS_OFFSET;
2794 port->rxfis_dma = port->block1_dma + AHCI_RX_FIS_OFFSET;
2795 port->identify = port->block1 + AHCI_IDFY_OFFSET;
2796 port->identify_dma = port->block1_dma + AHCI_IDFY_OFFSET;
2797 port->log_buf = port->block1 + AHCI_SECTBUF_OFFSET;
2798 port->log_buf_dma = port->block1_dma + AHCI_SECTBUF_OFFSET;
2799 port->smart_buf = port->block1 + AHCI_SMARTBUF_OFFSET;
2800 port->smart_buf_dma = port->block1_dma + AHCI_SMARTBUF_OFFSET;
2811 if (mtip_get_identify(dd->port, NULL) < 0)
2814 if (*(dd->port->identify + MTIP_FTL_REBUILD_OFFSET) ==
2816 set_bit(MTIP_PF_REBUILD_BIT, &dd->port->flags);
2819 mtip_dump_identify(dd->port);
2822 rv = mtip_read_log_page(dd->port, ATA_LOG_SATA_NCQ,
2823 dd->port->log_buf,
2824 dd->port->log_buf_dma, 1);
2830 buf = (unsigned char *)dd->port->log_buf;
2850 if (mtip_get_smart_attr(dd->port, 242, &attr242))
2885 dd->port = kzalloc_node(sizeof(struct mtip_port), GFP_KERNEL,
2887 if (!dd->port) {
2889 "Memory allocation: port structure\n");
2895 dd->work[i].port = dd->port;
2903 atomic_set(&dd->port->cmd_slot_unal, dd->unal_qdepth);
2907 spin_lock_init(&dd->port->cmd_issue_lock[i]);
2909 /* Set the port mmio base address. */
2910 dd->port->mmio = dd->mmio + PORT_OFFSET;
2911 dd->port->dd = dd;
2920 dd->port->s_active[i] =
2921 dd->port->mmio + i*0x80 + PORT_SCR_ACT;
2922 dd->port->cmd_issue[i] =
2923 dd->port->mmio + i*0x80 + PORT_COMMAND_ISSUE;
2924 dd->port->completed[i] =
2925 dd->port->mmio + i*0x80 + PORT_SDBV;
2930 while (((readl(dd->port->mmio + PORT_SCR_STAT) & 0x0F) != 0x03) &&
2965 mtip_init_port(dd->port);
2966 mtip_start_port(dd->port);
2982 init_waitqueue_head(&dd->port->svc_wait);
3001 mtip_deinit_port(dd->port);
3006 kfree(dd->port);
3015 if (dd->sr || !dd->port)
3021 if (!test_bit(MTIP_PF_REBUILD_BIT, &dd->port->flags) &&
3024 rv = mtip_standby_immediate(dd->port);
3043 /* de-initialize the port. */
3044 mtip_deinit_port(dd->port);
3060 kfree(dd->port);
3061 dd->port = NULL;
3115 mtip_deinit_port(dd->port);
3145 * Enable the port, DMA engine, and FIS reception specific
3148 mtip_init_port(dd->port);
3149 mtip_start_port(dd->port);
3385 if (unlikely(test_bit(MTIP_PF_SE_ACTIVE_BIT, &dd->port->flags))) {
3386 if (dd->port->ic_pause_timer) {
3387 unsigned long to = dd->port->ic_pause_timer +
3391 &dd->port->flags);
3393 dd->port->ic_pause_timer = 0;
3394 wake_up_interruptible(&dd->port->svc_wait);
3441 if (cmd->unaligned && atomic_dec_if_positive(&dd->port->cmd_slot_unal) >= 0)
3454 dd->port->command_list + sizeof(struct mtip_cmd_hdr) * rq->tag;
3457 if (mtip_commands_active(dd->port))
3461 if (test_bit(MTIP_PF_HOST_CAP_64, &dd->port->flags))
3480 mtip_issue_non_ncq_command(dd->port, rq->tag);
3547 if (test_bit(req->tag, dd->port->cmds_to_issue))
3550 if (test_and_set_bit(MTIP_PF_TO_ACTIVE_BIT, &dd->port->flags))
3553 wake_up_interruptible(&dd->port->svc_wait);
3776 set_bit(MTIP_PF_SVC_THD_STOP_BIT, &dd->port->flags);
3777 wake_up_interruptible(&dd->port->svc_wait);
3795 if (!mtip_quiesce_io(dd->port, MTIP_QUIESCE_IO_TIMEOUT_MS))