Lines Matching refs:pcie2
20 static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
22 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
23 pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
24 return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
28 static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
31 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
32 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
39 static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
45 val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
52 pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
54 return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
57 static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
60 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
61 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
63 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
64 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
66 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
67 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
70 static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
72 u8 core_rev = pcie2->core->id.rev;
78 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
80 devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
83 bcma_core_pcie2_set_ltr_vals(pcie2);
86 *si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0);
91 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
93 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
96 pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
101 pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
107 static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
109 u8 core_rev = pcie2->core->id.rev;
121 pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
124 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
126 pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
132 static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
134 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
135 pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
138 static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
140 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
141 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
144 static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
146 struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
147 u8 core_rev = pcie2->core->id.rev;
153 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
155 pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
159 void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
161 struct bcma_bus *bus = pcie2->core->bus;
165 tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
167 bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
172 pcie2->reqsize = 1024;
175 pcie2->reqsize = 128;
180 bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
181 bcma_core_pcie2_hw_ltr_war(pcie2);
182 pciedev_crwlpciegen2(pcie2);
183 pciedev_reg_pm_clk_period(pcie2);
184 pciedev_crwlpciegen2_180(pcie2);
185 pciedev_crwlpciegen2_182(pcie2);
192 void bcma_core_pcie2_up(struct bcma_drv_pcie2 *pcie2)
194 struct bcma_bus *bus = pcie2->core->bus;
198 err = pcie_set_readrq(dev, pcie2->reqsize);