Lines Matching defs:bytes
18 * bytes from the host to the internal register read/write on Avalon bus. In
20 * send formatted bytes that conform to the transfer protocol.
43 * layer bytes stream and then to physical layer bytes stream. Finally the
119 * In tx phase, the host prepares all the phy layer bytes of a request in the
128 * case, all transaction layer bytes need to be escaped (so the data length
135 * Unlike tx, phy rx is affected by possible PHY_IDLE bytes from slave, the max
146 * @word_len: bytes of word for spi transfer.
235 * phy_buf len should be aligned with SPI's BPW. Spare bytes should be padded
241 * time. As a result these rx bytes are lost. In the following case, 7a,7c,00
246 * So the driver moves EOP and bytes after EOP to the end of the aligned size,
328 /* move EOP and bytes after EOP to the end of aligned size */
598 static int regmap_spi_avmm_write(void *context, const void *data, size_t bytes)
600 if (bytes < SPI_AVMM_REG_SIZE + SPI_AVMM_VAL_SIZE)
605 bytes - SPI_AVMM_REG_SIZE);