Lines Matching defs:cache
3 // Register cache access API
57 dev_warn(map->dev, "No cache defaults, reading back from HW\n");
59 /* Bypass the cache access till data read from HW */
124 "No cache used with register defaults set!\n");
156 map->cache = NULL;
175 /* Some devices such as PMICs don't have cache defaults,
177 * crafting the cache defaults by hand.
190 dev_dbg(map->dev, "Initializing %s cache\n",
218 dev_dbg(map->dev, "Destroying %s cache\n",
225 * regcache_read - Fetch the value of a given register from the cache.
256 * regcache_write - Set the value of a given register in the cache.
329 * regcache_sync - Sync the register cache with the hardware.
354 dev_dbg(map->dev, "Syncing %s cache\n",
400 * regcache_sync_region - Sync part of the register cache with the hardware.
429 dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);
459 * regcache_drop_region - Discard part of the register cache
465 * Discard part of the register cache.
490 * regcache_cache_only - Put a register map into cache only mode
495 * When a register map is marked as cache only writes to the register
496 * map API will only update the register cache, they will not cause
518 * stored in the cache.
521 * the hardware state still matches the cache state, modulo any writes that
534 * regcache_cache_bypass - Put a register map into cache bypass mode
537 * @enable: flag if changes should not be written to the cache
539 * When a register map is marked with the cache bypass option, writes
541 * the cache directly. This is useful when syncing the cache back to
569 u8 *cache = base;
571 cache[idx] = val;
575 u16 *cache = base;
577 cache[idx] = val;
581 u32 *cache = base;
583 cache[idx] = val;
588 u64 *cache = base;
590 cache[idx] = val;
613 const u8 *cache = base;
615 return cache[idx];
618 const u16 *cache = base;
620 return cache[idx];
623 const u32 *cache = base;
625 return cache[idx];
629 const u64 *cache = base;
631 return cache[idx];