Lines Matching refs:card
26 * 1 - Per card interrupt spinlock (to protect structures and such)
28 * 3 - Per card resource spinlock (to access registers, etc.)
105 #define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ)
120 static u32 ns_read_sram(ns_dev * card, u32 sram_address);
121 static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
124 static void ns_init_card_error(ns_dev * card, int error);
125 static scq_info *get_scq(ns_dev *card, int size, u32 scd);
126 static void free_scq(ns_dev *card, scq_info * scq, struct atm_vcc *vcc);
131 static void fill_tst(ns_dev * card, int n, vc_map * vc);
133 static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
135 static void process_tsq(ns_dev * card);
136 static void drain_scq(ns_dev * card, scq_info * scq, int pos);
137 static void process_rsq(ns_dev * card);
138 static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe);
139 static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb);
140 static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count);
141 static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb);
142 static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb);
143 static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb);
147 static void which_list(ns_dev * card, struct sk_buff *skb);
199 ns_dev *card = pci_get_drvdata(pcidev);
205 i = card->index;
210 if (card->atmdev->phy && card->atmdev->phy->stop)
211 card->atmdev->phy->stop(card->atmdev);
214 writel(0x00000000, card->membase + CFG);
217 atm_dev_deregister(card->atmdev);
224 PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count);
225 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) {
232 card->iovpool.count);
233 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) {
238 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
240 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
242 free_scq(card, card->scq0, NULL);
244 if (card->scd2vc[j] != NULL)
245 free_scq(card, card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc);
247 idr_destroy(&card->idr);
248 dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
249 card->rsq.org, card->rsq.dma);
250 dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
251 card->tsq.org, card->tsq.dma);
252 free_irq(card->pcidev->irq, card);
253 iounmap(card->membase);
254 kfree(card);
307 static u32 ns_read_sram(ns_dev * card, u32 sram_address)
314 spin_lock_irqsave(&card->res_lock, flags);
315 while (CMD_BUSY(card)) ;
316 writel(sram_address, card->membase + CMD);
317 while (CMD_BUSY(card)) ;
318 data = readl(card->membase + DR0);
319 spin_unlock_irqrestore(&card->res_lock, flags);
323 static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value,
331 spin_lock_irqsave(&card->res_lock, flags);
332 while (CMD_BUSY(card)) ;
334 writel(*(value++), card->membase + i);
336 so card->membase + DR0 == card->membase */
340 writel(sram_address, card->membase + CMD);
341 spin_unlock_irqrestore(&card->res_lock, flags);
347 struct ns_dev *card = NULL;
361 ns_init_card_error(card, error);
368 ns_init_card_error(card, error);
372 card = kmalloc(sizeof(*card), GFP_KERNEL);
373 if (!card) {
378 ns_init_card_error(card, error);
381 cards[i] = card;
382 spin_lock_init(&card->int_lock);
383 spin_lock_init(&card->res_lock);
385 pci_set_drvdata(pcidev, card);
387 card->index = i;
388 card->atmdev = NULL;
389 card->pcidev = pcidev;
391 card->membase = ioremap(membase, NS_IOREMAP_SIZE);
392 if (!card->membase) {
395 ns_init_card_error(card, error);
398 PRINTK("nicstar%d: membase at 0x%p.\n", i, card->membase);
405 ns_init_card_error(card, error);
422 ns_init_card_error(card, error);
429 data = readl(card->membase + STAT);
431 writel(NS_STAT_TMROF, card->membase + STAT);
434 writel(NS_CFG_SWRST, card->membase + CFG);
436 writel(0x00000000, card->membase + CFG);
439 writel(0x00000008, card->membase + GP);
441 writel(0x00000001, card->membase + GP);
443 while (CMD_BUSY(card)) ;
444 writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */
448 while (CMD_BUSY(card)) ;
449 writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD);
450 while (CMD_BUSY(card)) ;
451 data = readl(card->membase + DR0);
455 card->max_pcr = ATM_25_PCR;
456 while (CMD_BUSY(card)) ;
457 writel(0x00000008, card->membase + DR0);
458 writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD);
460 writel(NS_STAT_SFBQF, card->membase + STAT);
462 while (CMD_BUSY(card)) ;
463 writel(0x00000022, card->membase + DR0);
464 writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD);
470 card->max_pcr = ATM_OC3_PCR;
472 while (CMD_BUSY(card)) ;
473 writel(0x00000002, card->membase + DR0);
474 writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD);
480 ns_init_card_error(card, error);
483 writel(0x00000000, card->membase + GP);
487 ns_write_sram(card, 0x1C003, &data, 1);
489 ns_write_sram(card, 0x14003, &data, 1);
490 if (ns_read_sram(card, 0x14003) == 0x89ABCDEF &&
491 ns_read_sram(card, 0x1C003) == 0x76543210)
492 card->sram_size = 128;
494 card->sram_size = 32;
495 PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size);
497 card->rct_size = NS_MAX_RCTSIZE;
500 if (card->sram_size == 128)
505 if (card->sram_size == 32) {
509 card->rct_size = 4096;
515 card->vpibits = NS_VPIBITS;
516 if (card->rct_size == 4096)
517 card->vcibits = 12 - NS_VPIBITS;
518 else /* card->rct_size == 16384 */
519 card->vcibits = 14 - NS_VPIBITS;
523 nicstar_init_eprom(card->membase);
526 writel(0x00000000, card->membase + VPM);
528 card->intcnt = 0;
530 (pcidev->irq, &ns_irq_handler, IRQF_SHARED, "nicstar", card) != 0) {
533 ns_init_card_error(card, error);
538 card->tsq.org = dma_alloc_coherent(&card->pcidev->dev,
540 &card->tsq.dma, GFP_KERNEL);
541 if (card->tsq.org == NULL) {
544 ns_init_card_error(card, error);
547 card->tsq.base = PTR_ALIGN(card->tsq.org, NS_TSQ_ALIGNMENT);
548 card->tsq.next = card->tsq.base;
549 card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1);
551 ns_tsi_init(card->tsq.base + j);
552 writel(0x00000000, card->membase + TSQH);
553 writel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), card->membase + TSQB);
554 PRINTK("nicstar%d: TSQ base at 0x%p.\n", i, card->tsq.base);
557 card->rsq.org = dma_alloc_coherent(&card->pcidev->dev,
559 &card->rsq.dma, GFP_KERNEL);
560 if (card->rsq.org == NULL) {
563 ns_init_card_error(card, error);
566 card->rsq.base = PTR_ALIGN(card->rsq.org, NS_RSQ_ALIGNMENT);
567 card->rsq.next = card->rsq.base;
568 card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1);
570 ns_rsqe_init(card->rsq.base + j);
571 writel(0x00000000, card->membase + RSQH);
572 writel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), card->membase + RSQB);
573 PRINTK("nicstar%d: RSQ base at 0x%p.\n", i, card->rsq.base);
576 card->scq1 = NULL;
577 card->scq2 = NULL;
578 card->scq0 = get_scq(card, VBR_SCQSIZE, NS_VRSCD0);
579 if (card->scq0 == NULL) {
582 ns_init_card_error(card, error);
585 u32d[0] = scq_virt_to_bus(card->scq0, card->scq0->base);
589 ns_write_sram(card, NS_VRSCD0, u32d, 4);
590 ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */
591 ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */
592 card->scq0->scd = NS_VRSCD0;
593 PRINTK("nicstar%d: VBR-SCQ0 base at 0x%p.\n", i, card->scq0->base);
596 card->tst_addr = NS_TST0;
597 card->tst_free_entries = NS_TST_NUM_ENTRIES;
600 ns_write_sram(card, NS_TST0 + j, &data, 1);
602 ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1);
604 ns_write_sram(card, NS_TST1 + j, &data, 1);
606 ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1);
608 card->tste2vc[j] = NULL;
609 writel(NS_TST0 << 2, card->membase + TSTB);
620 for (j = 0; j < card->rct_size; j++)
621 ns_write_sram(card, j * 4, u32d, 4);
623 memset(card->vcmap, 0, sizeof(card->vcmap));
626 card->scd2vc[j] = NULL;
629 card->sbnr.min = MIN_SB;
630 card->sbnr.init = NUM_SB;
631 card->sbnr.max = MAX_SB;
632 card->lbnr.min = MIN_LB;
633 card->lbnr.init = NUM_LB;
634 card->lbnr.max = MAX_LB;
635 card->iovnr.min = MIN_IOVB;
636 card->iovnr.init = NUM_IOVB;
637 card->iovnr.max = MAX_IOVB;
638 card->hbnr.min = MIN_HB;
639 card->hbnr.init = NUM_HB;
640 card->hbnr.max = MAX_HB;
642 card->sm_handle = NULL;
643 card->sm_addr = 0x00000000;
644 card->lg_handle = NULL;
645 card->lg_addr = 0x00000000;
647 card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */
649 idr_init(&card->idr);
652 skb_queue_head_init(&card->hbpool.queue);
653 card->hbpool.count = 0;
662 ns_init_card_error(card, error);
666 skb_queue_tail(&card->hbpool.queue, hb);
667 card->hbpool.count++;
671 skb_queue_head_init(&card->lbpool.queue);
672 card->lbpool.count = 0; /* Not used */
681 ns_init_card_error(card, error);
685 skb_queue_tail(&card->lbpool.queue, lb);
687 push_rxbufs(card, lb);
690 card->rcbuf = lb;
691 card->rawcell = (struct ns_rcqe *) lb->data;
692 card->rawch = NS_PRV_DMA(lb);
697 ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) {
702 ns_init_card_error(card, error);
707 skb_queue_head_init(&card->sbpool.queue);
708 card->sbpool.count = 0; /* Not used */
717 ns_init_card_error(card, error);
721 skb_queue_tail(&card->sbpool.queue, sb);
723 push_rxbufs(card, sb);
727 ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) {
732 ns_init_card_error(card, error);
737 skb_queue_head_init(&card->iovpool.queue);
738 card->iovpool.count = 0;
747 ns_init_card_error(card, error);
751 skb_queue_tail(&card->iovpool.queue, iovb);
752 card->iovpool.count++;
756 if (card->rct_size == 4096)
758 else /* (card->rct_size == 16384) */
761 card->efbie = 1;
764 card->atmdev = atm_dev_register("nicstar", &card->pcidev->dev, &atm_ops,
766 if (card->atmdev == NULL) {
769 ns_init_card_error(card, error);
773 if (mac[i] == NULL || !mac_pton(mac[i], card->atmdev->esi)) {
774 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET,
775 card->atmdev->esi, 6);
776 if (ether_addr_equal(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00")) {
777 nicstar_read_eprom(card->membase,
779 card->atmdev->esi, 6);
783 printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi);
785 card->atmdev->dev_data = card;
786 card->atmdev->ci_range.vpi_bits = card->vpibits;
787 card->atmdev->ci_range.vci_bits = card->vcibits;
788 card->atmdev->link_rate = card->max_pcr;
789 card->atmdev->phy = NULL;
792 if (card->max_pcr == ATM_OC3_PCR)
793 suni_init(card->atmdev);
797 if (card->max_pcr == ATM_25_PCR)
798 idt77105_init(card->atmdev);
801 if (card->atmdev->phy && card->atmdev->phy->start)
802 card->atmdev->phy->start(card->atmdev);
806 NS_CFG_PHYIE, card->membase + CFG);
813 static void ns_init_card_error(ns_dev *card, int error)
816 writel(0x00000000, card->membase + CFG);
820 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL)
825 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL)
827 free_scq(card, card->scq0, NULL);
831 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL)
836 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL)
840 dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT,
841 card->rsq.org, card->rsq.dma);
844 dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT,
845 card->tsq.org, card->tsq.dma);
848 free_irq(card->pcidev->irq, card);
851 iounmap(card->membase);
854 pci_disable_device(card->pcidev);
855 kfree(card);
859 static scq_info *get_scq(ns_dev *card, int size, u32 scd)
870 scq->org = dma_alloc_coherent(&card->pcidev->dev,
880 dma_free_coherent(&card->pcidev->dev,
904 static void free_scq(ns_dev *card, scq_info *scq, struct atm_vcc *vcc)
935 dma_free_coherent(&card->pcidev->dev,
944 static void push_rxbufs(ns_dev * card, struct sk_buff *skb)
956 addr1 = dma_map_single(&card->pcidev->dev,
966 card->index);
969 stat = readl(card->membase + STAT);
970 card->sbfqc = ns_stat_sfbqc_get(stat);
971 card->lbfqc = ns_stat_lfbqc_get(stat);
974 if (card->sm_addr) {
975 addr2 = card->sm_addr;
976 handle2 = card->sm_handle;
977 card->sm_addr = 0x00000000;
978 card->sm_handle = NULL;
981 card->sm_addr = addr1;
982 card->sm_handle = handle1;
988 if (card->lg_addr) {
989 addr2 = card->lg_addr;
990 handle2 = card->lg_handle;
991 card->lg_addr = 0x00000000;
992 card->lg_handle = NULL;
995 card->lg_addr = addr1;
996 card->lg_handle = handle1;
1003 if (card->sbfqc >= card->sbnr.max) {
1004 skb_unlink(handle1, &card->sbpool.queue);
1006 skb_unlink(handle2, &card->sbpool.queue);
1010 card->sbfqc += 2;
1013 if (card->lbfqc >= card->lbnr.max) {
1014 skb_unlink(handle1, &card->lbpool.queue);
1016 skb_unlink(handle2, &card->lbpool.queue);
1020 card->lbfqc += 2;
1023 id1 = idr_alloc(&card->idr, handle1, 0, 0, GFP_ATOMIC);
1027 id2 = idr_alloc(&card->idr, handle2, 0, 0, GFP_ATOMIC);
1031 spin_lock_irqsave(&card->res_lock, flags);
1032 while (CMD_BUSY(card)) ;
1033 writel(addr2, card->membase + DR3);
1034 writel(id2, card->membase + DR2);
1035 writel(addr1, card->membase + DR1);
1036 writel(id1, card->membase + DR0);
1038 card->membase + CMD);
1039 spin_unlock_irqrestore(&card->res_lock, flags);
1042 card->index,
1047 if (!card->efbie && card->sbfqc >= card->sbnr.min &&
1048 card->lbfqc >= card->lbnr.min) {
1049 card->efbie = 1;
1050 writel((readl(card->membase + CFG) | NS_CFG_EFBIE),
1051 card->membase + CFG);
1061 ns_dev *card;
1065 card = (ns_dev *) dev_id;
1066 dev = card->atmdev;
1067 card->intcnt++;
1069 PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index);
1071 spin_lock_irqsave(&card->int_lock, flags);
1073 stat_r = readl(card->membase + STAT);
1077 TXPRINTK("nicstar%d: TSI interrupt\n", card->index);
1078 process_tsq(card);
1079 writel(NS_STAT_TSIF, card->membase + STAT);
1084 writel(NS_STAT_TXICP, card->membase + STAT);
1086 card->index);
1091 writel(NS_STAT_TSQF, card->membase + STAT);
1092 PRINTK("nicstar%d: TSQ full.\n", card->index);
1093 process_tsq(card);
1098 writel(NS_STAT_TMROF, card->membase + STAT);
1099 PRINTK("nicstar%d: Timer overflow.\n", card->index);
1104 writel(NS_STAT_PHYI, card->membase + STAT);
1105 PRINTK("nicstar%d: PHY interrupt.\n", card->index);
1113 writel(NS_STAT_SFBQF, card->membase + STAT);
1115 card->index);
1120 writel(NS_STAT_LFBQF, card->membase + STAT);
1122 card->index);
1127 writel(NS_STAT_RSQF, card->membase + STAT);
1128 printk("nicstar%d: RSQ full.\n", card->index);
1129 process_rsq(card);
1134 RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index);
1135 process_rsq(card);
1136 writel(NS_STAT_EOPDU, card->membase + STAT);
1141 writel(NS_STAT_RAWCF, card->membase + STAT);
1144 card->index);
1149 while (readl(card->membase + RAWCT) != card->rawch) {
1151 if (ns_rcqe_islast(card->rawcell)) {
1154 oldbuf = card->rcbuf;
1155 card->rcbuf = idr_find(&card->idr,
1156 ns_rcqe_nextbufhandle(card->rawcell));
1157 card->rawch = NS_PRV_DMA(card->rcbuf);
1158 card->rawcell = (struct ns_rcqe *)
1159 card->rcbuf->data;
1160 recycle_rx_buf(card, oldbuf);
1162 card->rawch += NS_RCQE_SIZE;
1163 card->rawcell++;
1173 writel(NS_STAT_SFBQE, card->membase + STAT);
1175 card->index);
1176 for (i = 0; i < card->sbnr.min; i++) {
1179 writel(readl(card->membase + CFG) &
1180 ~NS_CFG_EFBIE, card->membase + CFG);
1181 card->efbie = 0;
1185 skb_queue_tail(&card->sbpool.queue, sb);
1187 push_rxbufs(card, sb);
1189 card->sbfqc = i;
1190 process_rsq(card);
1198 writel(NS_STAT_LFBQE, card->membase + STAT);
1200 card->index);
1201 for (i = 0; i < card->lbnr.min; i++) {
1204 writel(readl(card->membase + CFG) &
1205 ~NS_CFG_EFBIE, card->membase + CFG);
1206 card->efbie = 0;
1210 skb_queue_tail(&card->lbpool.queue, lb);
1212 push_rxbufs(card, lb);
1214 card->lbfqc = i;
1215 process_rsq(card);
1220 writel(NS_STAT_RSQAF, card->membase + STAT);
1221 RXPRINTK("nicstar%d: RSQ almost full.\n", card->index);
1222 process_rsq(card);
1225 spin_unlock_irqrestore(&card->int_lock, flags);
1226 PRINTK("nicstar%d: end of interrupt service\n", card->index);
1232 ns_dev *card;
1247 card = (ns_dev *) vcc->dev->dev_data;
1248 PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int)vpi,
1251 PRINTK("nicstar%d: unsupported AAL.\n", card->index);
1255 vc = &(card->vcmap[vpi << card->vcibits | vci]);
1264 printk("nicstar%d: %s vci already in use.\n", card->index,
1284 card->index);
1294 card->index, vcc->qos.txtp.max_pcr);
1299 modl = tmpl % card->max_pcr;
1301 n = (int)(tmpl / card->max_pcr);
1307 (card->tst_free_entries -
1311 card->index);
1321 card->index);
1327 if (n > (card->tst_free_entries - NS_TST_RESERVED)) {
1330 card->index);
1335 card->tst_free_entries -= n;
1338 card->index, n);
1340 if (card->scd2vc[frscdi] == NULL) {
1341 card->scd2vc[frscdi] = vc;
1348 card->index);
1349 card->tst_free_entries += n;
1357 scq = get_scq(card, CBR_SCQSIZE, vc->cbr_scd);
1360 card->index);
1361 card->scd2vc[frscdi] = NULL;
1362 card->tst_free_entries += n;
1372 ns_write_sram(card, vc->cbr_scd, u32d, 4);
1374 fill_tst(card, n, vc);
1377 vc->scq = card->scq0;
1400 ns_write_sram(card,
1402 (vpi << card->vcibits | vci) *
1415 ns_dev *card;
1420 card = vcc->dev->dev_data;
1421 PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index,
1432 (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE;
1433 spin_lock_irqsave(&card->res_lock, flags);
1434 while (CMD_BUSY(card)) ;
1436 card->membase + CMD);
1437 spin_unlock_irqrestore(&card->res_lock, flags);
1444 stat = readl(card->membase + STAT);
1445 card->sbfqc = ns_stat_sfbqc_get(stat);
1446 card->lbfqc = ns_stat_lfbqc_get(stat);
1450 card->index);
1452 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
1455 spin_lock_irqsave(&card->int_lock, flags);
1456 recycle_iov_buf(card, iovb);
1457 spin_unlock_irqrestore(&card->int_lock, flags);
1506 ns_write_sram(card, scq->scd, &data, 1);
1515 if (card->tste2vc[i] == vc) {
1516 ns_write_sram(card, card->tst_addr + i, &data,
1518 card->tste2vc[i] = NULL;
1519 card->tst_free_entries++;
1523 card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL;
1524 free_scq(card, vc->scq, vcc);
1530 scq_info *scq = card->scq0;
1553 stat = readl(card->membase + STAT);
1554 cfg = readl(card->membase + CFG);
1558 card->tsq.base, card->tsq.next,
1559 card->tsq.last, readl(card->membase + TSQT));
1562 card->rsq.base, card->rsq.next,
1563 card->rsq.last, readl(card->membase + RSQT));
1565 card->efbie ? "enabled" : "disabled");
1567 ns_stat_sfbqc_get(stat), card->sbpool.count,
1568 ns_stat_lfbqc_get(stat), card->lbpool.count);
1570 card->hbpool.count, card->iovpool.count);
1575 static void fill_tst(ns_dev * card, int n, vc_map * vc)
1586 new_tst = card->tst_addr;
1591 if (card->tste2vc[e] == NULL)
1595 printk("nicstar%d: No free TST entries found. \n", card->index);
1604 if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) {
1605 card->tste2vc[e] = vc;
1606 ns_write_sram(card, new_tst + e, &data, 1);
1620 ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1);
1621 ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1);
1622 card->tst_addr = new_tst;
1627 ns_dev *card;
1634 card = vcc->dev->dev_data;
1635 TXPRINTK("nicstar%d: ns_send() called.\n", card->index);
1638 card->index);
1646 card->index);
1654 card->index);
1661 printk("nicstar%d: No scatter-gather yet.\n", card->index);
1669 NS_PRV_DMA(skb) = dma_map_single(&card->pcidev->dev, skb->data,
1706 scq = card->scq0;
1709 if (push_scqe(card, vc, scq, &scqe, skb) != 0) {
1711 dma_unmap_single(&card->pcidev->dev, NS_PRV_DMA(skb), skb->len,
1721 static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd,
1735 printk("nicstar%d: Error pushing TBD.\n", card->index);
1748 card->index);
1756 card->index, skb, index);
1758 card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2),
1780 ns_write_sram(card, scq->scd, &data, 1);
1783 card->index);
1812 card->index, le32_to_cpu(tsr.word_1),
1823 card->index);
1826 ns_write_sram(card, scq->scd, &data, 1);
1833 static void process_tsq(ns_dev * card)
1842 if (card->tsq.next == card->tsq.last)
1843 one_ahead = card->tsq.base;
1845 one_ahead = card->tsq.next + 1;
1847 if (one_ahead == card->tsq.last)
1848 two_ahead = card->tsq.base;
1852 while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) ||
1859 while (ns_tsi_isempty(card->tsq.next)) {
1860 if (card->tsq.next == card->tsq.last)
1861 card->tsq.next = card->tsq.base;
1863 card->tsq.next++;
1866 if (!ns_tsi_tmrof(card->tsq.next)) {
1867 scdi = ns_tsi_getscdindex(card->tsq.next);
1869 scq = card->scq0;
1871 if (card->scd2vc[scdi] == NULL) {
1874 card->index);
1875 ns_tsi_init(card->tsq.next);
1878 scq = card->scd2vc[scdi]->scq;
1880 drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next));
1885 ns_tsi_init(card->tsq.next);
1886 previous = card->tsq.next;
1887 if (card->tsq.next == card->tsq.last)
1888 card->tsq.next = card->tsq.base;
1890 card->tsq.next++;
1892 if (card->tsq.next == card->tsq.last)
1893 one_ahead = card->tsq.base;
1895 one_ahead = card->tsq.next + 1;
1897 if (one_ahead == card->tsq.last)
1898 two_ahead = card->tsq.base;
1904 writel(PTR_DIFF(previous, card->tsq.base),
1905 card->membase + TSQH);
1908 static void drain_scq(ns_dev * card, scq_info * scq, int pos)
1916 card->index, scq, pos);
1918 printk("nicstar%d: Bad index on drain_scq().\n", card->index);
1929 card->index, skb, i);
1931 dma_unmap_single(&card->pcidev->dev,
1950 static void process_rsq(ns_dev * card)
1954 if (!ns_rsqe_valid(card->rsq.next))
1957 dequeue_rx(card, card->rsq.next);
1958 ns_rsqe_init(card->rsq.next);
1959 previous = card->rsq.next;
1960 if (card->rsq.next == card->rsq.last)
1961 card->rsq.next = card->rsq.base;
1963 card->rsq.next++;
1964 } while (ns_rsqe_valid(card->rsq.next));
1965 writel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH);
1968 static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe)
1981 stat = readl(card->membase + STAT);
1982 card->sbfqc = ns_stat_sfbqc_get(stat);
1983 card->lbfqc = ns_stat_lfbqc_get(stat);
1986 skb = idr_remove(&card->idr, id);
1989 "nicstar%d: skb not found!\n", card->index);
1992 dma_sync_single_for_cpu(&card->pcidev->dev,
1997 dma_unmap_single(&card->pcidev->dev,
2004 if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) {
2006 card->index, vpi, vci);
2007 recycle_rx_buf(card, skb);
2011 vc = &(card->vcmap[vpi << card->vcibits | vci]);
2014 card->index, vpi, vci);
2015 recycle_rx_buf(card, skb);
2032 card->index);
2039 card->index);
2059 recycle_rx_buf(card, skb);
2066 iovb = skb_dequeue(&(card->iovpool.queue));
2071 card->index);
2073 recycle_rx_buf(card, skb);
2077 } else if (--card->iovpool.count < card->iovnr.min) {
2082 skb_queue_tail(&card->iovpool.queue, new_iovb);
2083 card->iovpool.count++;
2095 printk("nicstar%d: received too big AAL5 SDU.\n", card->index);
2097 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2114 card->index);
2115 which_list(card, skb);
2117 recycle_rx_buf(card, skb);
2119 recycle_iov_buf(card, iovb);
2127 card->index);
2128 which_list(card, skb);
2130 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2133 recycle_iov_buf(card, iovb);
2147 printk("nicstar%d: AAL5 CRC error", card->index);
2153 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data,
2156 recycle_iov_buf(card, iovb);
2165 push_rxbufs(card, skb);
2169 dequeue_sm_buf(card, skb);
2183 push_rxbufs(card, sb);
2187 dequeue_sm_buf(card, sb);
2194 push_rxbufs(card, skb);
2199 push_rxbufs(card, skb);
2202 dequeue_lg_buf(card, skb);
2213 push_rxbufs(card, sb);
2223 hb = skb_dequeue(&(card->hbpool.queue));
2230 card->index);
2232 recycle_iovec_rx_bufs(card,
2237 recycle_iov_buf(card, iovb);
2239 } else if (card->hbpool.count < card->hbnr.min) {
2244 skb_queue_tail(&card->hbpool.
2246 card->hbpool.count++;
2250 } else if (--card->hbpool.count < card->hbnr.min) {
2255 skb_queue_tail(&card->hbpool.queue,
2257 card->hbpool.count++;
2259 if (card->hbpool.count < card->hbnr.min) {
2265 skb_queue_tail(&card->hbpool.
2267 card->hbpool.count++;
2275 recycle_iovec_rx_bufs(card, iov,
2277 if (card->hbpool.count < card->hbnr.max) {
2278 skb_queue_tail(&card->hbpool.queue, hb);
2279 card->hbpool.count++;
2292 push_rxbufs(card, sb);
2305 push_rxbufs(card, lb);
2311 card->index);
2321 recycle_iov_buf(card, iovb);
2326 static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb)
2330 card->index);
2333 push_rxbufs(card, skb);
2336 static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count)
2339 recycle_rx_buf(card, (struct sk_buff *)(iov++)->iov_base);
2342 static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb)
2344 if (card->iovpool.count < card->iovnr.max) {
2345 skb_queue_tail(&card->iovpool.queue, iovb);
2346 card->iovpool.count++;
2351 static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb)
2353 skb_unlink(sb, &card->sbpool.queue);
2354 if (card->sbfqc < card->sbnr.init) {
2358 skb_queue_tail(&card->sbpool.queue, new_sb);
2360 push_rxbufs(card, new_sb);
2363 if (card->sbfqc < card->sbnr.init)
2368 skb_queue_tail(&card->sbpool.queue, new_sb);
2370 push_rxbufs(card, new_sb);
2375 static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb)
2377 skb_unlink(lb, &card->lbpool.queue);
2378 if (card->lbfqc < card->lbnr.init) {
2382 skb_queue_tail(&card->lbpool.queue, new_lb);
2384 push_rxbufs(card, new_lb);
2387 if (card->lbfqc < card->lbnr.init)
2392 skb_queue_tail(&card->lbpool.queue, new_lb);
2394 push_rxbufs(card, new_lb);
2402 ns_dev *card;
2406 card = (ns_dev *) dev->dev_data;
2407 stat = readl(card->membase + STAT);
2412 ns_stat_sfbqc_get(stat), card->sbnr.min,
2413 card->sbnr.init, card->sbnr.max);
2416 ns_stat_lfbqc_get(stat), card->lbnr.min,
2417 card->lbnr.init, card->lbnr.max);
2420 card->hbpool.count, card->hbnr.min,
2421 card->hbnr.init, card->hbnr.max);
2424 card->iovpool.count, card->iovnr.min,
2425 card->iovnr.init, card->iovnr.max);
2429 sprintf(page, "Interrupt counter: %u \n", card->intcnt);
2430 card->intcnt = 0;
2437 if (card->max_pcr == ATM_25_PCR && !left--) {
2442 while (CMD_BUSY(card)) ;
2444 card->membase + CMD);
2445 while (CMD_BUSY(card)) ;
2446 phy_regs[i] = readl(card->membase + DR0) & 0x000000FF;
2457 if (card->tste2vc[left + 1] == NULL)
2461 card->tste2vc[left + 1]->tx_vcc->vpi,
2462 card->tste2vc[left + 1]->tx_vcc->vci);
2470 ns_dev *card;
2475 card = dev->dev_data;
2484 ns_stat_sfbqc_get(readl(card->membase + STAT));
2485 pl.level.min = card->sbnr.min;
2486 pl.level.init = card->sbnr.init;
2487 pl.level.max = card->sbnr.max;
2492 ns_stat_lfbqc_get(readl(card->membase + STAT));
2493 pl.level.min = card->lbnr.min;
2494 pl.level.init = card->lbnr.init;
2495 pl.level.max = card->lbnr.max;
2499 pl.count = card->hbpool.count;
2500 pl.level.min = card->hbnr.min;
2501 pl.level.init = card->hbnr.init;
2502 pl.level.max = card->hbnr.max;
2506 pl.count = card->iovpool.count;
2507 pl.level.min = card->iovnr.min;
2508 pl.level.init = card->iovnr.init;
2509 pl.level.max = card->iovnr.max;
2535 card->sbnr.min = pl.level.min;
2536 card->sbnr.init = pl.level.init;
2537 card->sbnr.max = pl.level.max;
2543 card->lbnr.min = pl.level.min;
2544 card->lbnr.init = pl.level.init;
2545 card->lbnr.max = pl.level.max;
2551 card->hbnr.min = pl.level.min;
2552 card->hbnr.init = pl.level.init;
2553 card->hbnr.max = pl.level.max;
2559 card->iovnr.min = pl.level.min;
2560 card->iovnr.init = pl.level.init;
2561 card->iovnr.max = pl.level.max;
2576 while (card->sbfqc < card->sbnr.init) {
2583 skb_queue_tail(&card->sbpool.queue, sb);
2585 push_rxbufs(card, sb);
2590 while (card->lbfqc < card->lbnr.init) {
2597 skb_queue_tail(&card->lbpool.queue, lb);
2599 push_rxbufs(card, lb);
2604 while (card->hbpool.count > card->hbnr.init) {
2607 spin_lock_irqsave(&card->int_lock, flags);
2608 hb = skb_dequeue(&card->hbpool.queue);
2609 card->hbpool.count--;
2610 spin_unlock_irqrestore(&card->int_lock, flags);
2614 card->index);
2619 while (card->hbpool.count < card->hbnr.init) {
2626 spin_lock_irqsave(&card->int_lock, flags);
2627 skb_queue_tail(&card->hbpool.queue, hb);
2628 card->hbpool.count++;
2629 spin_unlock_irqrestore(&card->int_lock, flags);
2634 while (card->iovpool.count > card->iovnr.init) {
2637 spin_lock_irqsave(&card->int_lock, flags);
2638 iovb = skb_dequeue(&card->iovpool.queue);
2639 card->iovpool.count--;
2640 spin_unlock_irqrestore(&card->int_lock, flags);
2644 card->index);
2649 while (card->iovpool.count < card->iovnr.init) {
2656 spin_lock_irqsave(&card->int_lock, flags);
2657 skb_queue_tail(&card->iovpool.queue, iovb);
2658 card->iovpool.count++;
2659 spin_unlock_irqrestore(&card->int_lock, flags);
2673 printk("nicstar%d: %s == NULL \n", card->index,
2681 static void which_list(ns_dev * card, struct sk_buff *skb)
2690 ns_dev *card;
2696 card = cards[i];
2697 if (!spin_trylock_irqsave(&card->int_lock, flags)) {
2703 stat_r = readl(card->membase + STAT);
2709 process_tsq(card);
2710 process_rsq(card);
2712 writel(stat_w, card->membase + STAT);
2713 spin_unlock_irqrestore(&card->int_lock, flags);
2722 ns_dev *card;
2725 card = dev->dev_data;
2726 spin_lock_irqsave(&card->res_lock, flags);
2727 while (CMD_BUSY(card)) ;
2728 writel((u32) value, card->membase + DR0);
2730 card->membase + CMD);
2731 spin_unlock_irqrestore(&card->res_lock, flags);
2736 ns_dev *card;
2740 card = dev->dev_data;
2741 spin_lock_irqsave(&card->res_lock, flags);
2742 while (CMD_BUSY(card)) ;
2744 card->membase + CMD);
2745 while (CMD_BUSY(card)) ;
2746 data = readl(card->membase + DR0) & 0x000000FF;
2747 spin_unlock_irqrestore(&card->res_lock, flags);