Lines Matching defs:lanai
2 /* lanai.c -- Copyright 1999-2003 by Mitchell Blank Jr <mitch@sfgoth.com>
160 #define DEV_LABEL "lanai"
302 static void vci_bitfield_iterate(struct lanai_dev *lanai,
309 func(lanai, vci);
333 if (bytes > (128 * 1024)) /* max lanai buffer size */
342 * everything, but the way the lanai uses DMA memory would
439 #define CONFIG1_GPOUT3 (0x00004000) /* Loopback lanai */
468 static inline bus_addr_t reg_addr(const struct lanai_dev *lanai,
471 return lanai->base + reg;
474 static inline u32 reg_read(const struct lanai_dev *lanai,
478 t = readl(reg_addr(lanai, reg));
479 RWDEBUG("R [0x%08X] 0x%02X = 0x%08X\n", (unsigned int) lanai->base,
484 static inline void reg_write(const struct lanai_dev *lanai, u32 val,
487 RWDEBUG("W [0x%08X] 0x%02X < 0x%08X\n", (unsigned int) lanai->base,
489 writel(val, reg_addr(lanai, reg));
492 static inline void conf1_write(const struct lanai_dev *lanai)
494 reg_write(lanai, lanai->conf1, Config1_Reg);
497 static inline void conf2_write(const struct lanai_dev *lanai)
499 reg_write(lanai, lanai->conf2, Config2_Reg);
503 static inline void conf2_write_if_powerup(const struct lanai_dev *lanai)
506 if (unlikely((lanai->conf1 & CONFIG1_POWERDOWN) != 0))
509 conf2_write(lanai);
512 static inline void reset_board(const struct lanai_dev *lanai)
515 reg_write(lanai, 0, Reset_Reg);
535 static inline bus_addr_t sram_addr(const struct lanai_dev *lanai, int offset)
537 return lanai->base + SRAM_START + offset;
540 static inline u32 sram_read(const struct lanai_dev *lanai, int offset)
542 return readl(sram_addr(lanai, offset));
545 static inline void sram_write(const struct lanai_dev *lanai,
548 writel(val, sram_addr(lanai, offset));
551 static int sram_test_word(const struct lanai_dev *lanai, int offset,
555 sram_write(lanai, pattern, offset);
556 readback = sram_read(lanai, offset);
561 lanai->number, offset,
566 static int sram_test_pass(const struct lanai_dev *lanai, u32 pattern)
570 result = sram_test_word(lanai, offset, pattern);
574 static int sram_test_and_clear(const struct lanai_dev *lanai)
579 if ((result = sram_test_pass(lanai, 0x5555)) != 0)
581 if ((result = sram_test_pass(lanai, 0xAAAA)) != 0)
585 return sram_test_pass(lanai, 0x0000);
640 static inline bus_addr_t cardvcc_addr(const struct lanai_dev *lanai,
643 return sram_addr(lanai, vci * CARDVCC_SIZE);
756 * Unfortunately the lanai needs us to wait until all the data
762 static void lanai_shutdown_tx_vci(struct lanai_dev *lanai,
776 __clear_bit(lvcc->vci, lanai->backlog_vccs);
818 static inline int aal0_buffer_allocate(struct lanai_dev *lanai)
821 lanai_buf_allocate(&lanai->aal0buf, AAL0_RX_BUFFER_SIZE, 80,
822 lanai->pci);
823 return (lanai->aal0buf.start == NULL) ? -ENOMEM : 0;
826 static inline void aal0_buffer_free(struct lanai_dev *lanai)
829 lanai_buf_deallocate(&lanai->aal0buf, lanai->pci);
851 static int eeprom_read(struct lanai_dev *lanai)
854 lanai->number);
855 memset(&lanai->eeprom[EEPROM_MAC], 0, 6);
859 static int eeprom_validate(struct lanai_dev *lanai)
861 lanai->serialno = 0;
862 lanai->magicno = EEPROM_MAGIC_VALUE;
868 static int eeprom_read(struct lanai_dev *lanai)
873 #define set_config1(x) do { lanai->conf1 = x; conf1_write(lanai); \
875 #define clock_h() set_config1(lanai->conf1 | CONFIG1_PROMCLK)
876 #define clock_l() set_config1(lanai->conf1 &~ CONFIG1_PROMCLK)
877 #define data_h() set_config1(lanai->conf1 | CONFIG1_PROMDATA)
878 #define data_l() set_config1(lanai->conf1 &~ CONFIG1_PROMDATA)
880 #define read_pin() (reg_read(lanai, Status_Reg) & STATUS_PROMDATA)
891 tmp = (lanai->conf1 & ~CONFIG1_PROMDATA) |
893 if (lanai->conf1 != tmp) {
916 lanai->eeprom[address] = data;
925 lanai->number, address);
938 static inline u32 eeprom_be4(const struct lanai_dev *lanai, int address)
940 return be32_to_cpup((const u32 *) &lanai->eeprom[address]);
944 static int eeprom_validate(struct lanai_dev *lanai)
948 const u8 *e = lanai->eeprom;
968 "(wanted 0x%02X, got 0x%02X)\n", lanai->number,
975 "bad (wanted 0x%02X, got 0x%02X)\n", lanai->number,
984 "(0x%02X, inverse 0x%02X)\n", lanai->number,
991 lanai->serialno = eeprom_be4(lanai, EEPROM_SERIAL);
992 v = eeprom_be4(lanai, EEPROM_SERIAL_REV);
993 if ((lanai->serialno ^ v) != 0xFFFFFFFF) {
995 "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
996 (unsigned int) lanai->serialno, (unsigned int) v);
999 DPRINTK("eeprom: Serial number = %d\n", (unsigned int) lanai->serialno);
1001 lanai->magicno = eeprom_be4(lanai, EEPROM_MAGIC);
1002 v = eeprom_be4(lanai, EEPROM_MAGIC_REV);
1003 if ((lanai->magicno ^ v) != 0xFFFFFFFF) {
1005 "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
1006 lanai->magicno, v);
1009 DPRINTK("eeprom: Magic number = 0x%08X\n", lanai->magicno);
1010 if (lanai->magicno != EEPROM_MAGIC_VALUE)
1013 lanai->number, (unsigned int) lanai->magicno,
1020 static inline const u8 *eeprom_mac(const struct lanai_dev *lanai)
1022 return &lanai->eeprom[EEPROM_MAC];
1041 #define INT_TABORTSENT (0x00004000) /* Target abort sent by lanai */
1052 static inline u32 intr_pending(const struct lanai_dev *lanai)
1054 return reg_read(lanai, IntStatusMasked_Reg);
1057 static inline void intr_enable(const struct lanai_dev *lanai, u32 i)
1059 reg_write(lanai, i, IntControlEna_Reg);
1062 static inline void intr_disable(const struct lanai_dev *lanai, u32 i)
1064 reg_write(lanai, i, IntControlDis_Reg);
1076 static void lanai_check_status(struct lanai_dev *lanai)
1078 u32 new = reg_read(lanai, Status_Reg);
1079 u32 changes = new ^ lanai->status;
1080 lanai->status = new;
1083 status_message(lanai->number, name, new & flag)
1096 static void pcistatus_check(struct lanai_dev *lanai, int clearonly)
1100 result = pci_read_config_word(lanai->pci, PCI_STATUS, &s);
1103 "%d\n", lanai->number, result);
1111 result = pci_write_config_word(lanai->pci, PCI_STATUS, s);
1114 "%d\n", lanai->number, result);
1119 pcistatus_got(lanai->number, name); \
1120 ++lanai->stats.pcierr_##stat; \
1233 static inline void lanai_endtx(struct lanai_dev *lanai,
1249 spin_lock(&lanai->endtxlock);
1256 for (i = 0; reg_read(lanai, Status_Reg) & STATUS_BUTTBUSY; i++) {
1259 "always busy!\n", lanai->number);
1270 reg_write(lanai, (ptr << 12) | lvcc->vci, Butt_Reg);
1271 spin_unlock(&lanai->endtxlock);
1278 static void lanai_send_one_aal5(struct lanai_dev *lanai,
1292 lanai_endtx(lanai, lvcc);
1298 static void vcc_tx_unqueue_aal5(struct lanai_dev *lanai,
1317 lanai_send_one_aal5(lanai, lvcc, skb, n);
1322 __clear_bit(lvcc->vci, lanai->backlog_vccs);
1327 static void vcc_tx_aal5(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1338 __set_bit(lvcc->vci, lanai->backlog_vccs);
1343 lanai_send_one_aal5(lanai, lvcc, skb, n);
1346 static void vcc_tx_unqueue_aal0(struct lanai_dev *lanai,
1353 static void vcc_tx_aal0(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1423 static void vcc_rx_aal0(struct lanai_dev *lanai)
1439 static int vcc_table_allocate(struct lanai_dev *lanai)
1442 APRINTK((lanai->num_vci) * sizeof(struct lanai_vcc *) <= PAGE_SIZE,
1444 lanai->vccs = (struct lanai_vcc **) get_zeroed_page(GFP_KERNEL);
1445 return (lanai->vccs == NULL) ? -ENOMEM : 0;
1447 int bytes = (lanai->num_vci) * sizeof(struct lanai_vcc *);
1448 lanai->vccs = vzalloc(bytes);
1449 if (unlikely(lanai->vccs == NULL))
1455 static inline void vcc_table_deallocate(const struct lanai_dev *lanai)
1458 free_page((unsigned long) lanai->vccs);
1460 vfree(lanai->vccs);
1478 static int lanai_get_sized_buffer(struct lanai_dev *lanai,
1487 lanai_buf_allocate(buf, size, max_sdu + 32, lanai->pci);
1492 "for %s buffer, got only %zu\n", lanai->number, size,
1499 static inline int lanai_setup_rx_vci_aal5(struct lanai_dev *lanai,
1502 return lanai_get_sized_buffer(lanai, &lvcc->rx.buf,
1507 static int lanai_setup_tx_vci(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1520 return lanai_get_sized_buffer(lanai, &lvcc->tx.buf, max_sdu,
1524 static inline void host_vcc_bind(struct lanai_dev *lanai,
1531 if (lanai->nbound++ == 0) {
1533 lanai->conf1 &= ~CONFIG1_POWERDOWN;
1534 conf1_write(lanai);
1535 conf2_write(lanai);
1538 lvcc->vbase = cardvcc_addr(lanai, vci);
1539 lanai->vccs[lvcc->vci = vci] = lvcc;
1542 static inline void host_vcc_unbind(struct lanai_dev *lanai,
1549 lanai->vccs[lvcc->vci] = NULL;
1551 if (--lanai->nbound == 0) {
1553 lanai->conf1 |= CONFIG1_POWERDOWN;
1554 conf1_write(lanai);
1561 static void lanai_reset(struct lanai_dev *lanai)
1564 "implemented\n", lanai->number);
1570 reg_write(lanai, INT_ALL, IntAck_Reg);
1571 lanai->stats.card_reset++;
1579 static int service_buffer_allocate(struct lanai_dev *lanai)
1581 lanai_buf_allocate(&lanai->service, SERVICE_ENTRIES * 4, 8,
1582 lanai->pci);
1583 if (unlikely(lanai->service.start == NULL))
1586 lanai->service.start,
1587 lanai_buf_size(&lanai->service),
1588 lanai_buf_size_cardorder(&lanai->service));
1590 reg_write(lanai, 0, ServWrite_Reg);
1592 reg_write(lanai,
1593 SSTUFF_SET_SIZE(lanai_buf_size_cardorder(&lanai->service)) |
1594 SSTUFF_SET_ADDR(lanai->service.dmaaddr),
1599 static inline void service_buffer_deallocate(struct lanai_dev *lanai)
1601 lanai_buf_deallocate(&lanai->service, lanai->pci);
1617 static int handle_service(struct lanai_dev *lanai, u32 s)
1622 lvcc = lanai->vccs[vci];
1626 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1628 lanai->stats.service_notx++;
1630 lanai->stats.service_norx++;
1637 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1638 lanai->stats.service_notx++;
1641 __set_bit(vci, lanai->transmit_ready);
1649 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1650 lanai->stats.service_norx++;
1656 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1657 lanai->stats.service_rxnotaal5++;
1677 lanai->stats.ovfl_trash += (bytes / 48);
1685 "PDU on VCI %d!\n", lanai->number, vci);
1686 lanai_reset(lanai);
1699 static void iter_transmit(struct lanai_dev *lanai, vci_t vci)
1701 struct lanai_vcc *lvcc = lanai->vccs[vci];
1703 lvcc->tx.unqueue(lanai, lvcc, lvcc->tx.endptr);
1707 * interrupts otherwise disabled and with the lanai->servicelock
1710 static void run_service(struct lanai_dev *lanai)
1713 u32 wreg = reg_read(lanai, ServWrite_Reg);
1714 const u32 *end = lanai->service.start + wreg;
1715 while (lanai->service.ptr != end) {
1716 ntx += handle_service(lanai,
1717 le32_to_cpup(lanai->service.ptr++));
1718 if (lanai->service.ptr >= lanai->service.end)
1719 lanai->service.ptr = lanai->service.start;
1721 reg_write(lanai, wreg, ServRead_Reg);
1724 vci_bitfield_iterate(lanai, lanai->transmit_ready,
1726 bitmap_zero(lanai->transmit_ready, NUM_VCI);
1733 static void get_statistics(struct lanai_dev *lanai)
1735 u32 statreg = reg_read(lanai, Statistics_Reg);
1736 lanai->stats.atm_ovfl += STATS_GET_FIFO_OVFL(statreg);
1737 lanai->stats.hec_err += STATS_GET_HEC_ERR(statreg);
1738 lanai->stats.vci_trash += STATS_GET_BAD_VCI(statreg);
1739 lanai->stats.ovfl_trash += STATS_GET_BUF_OVFL(statreg);
1746 static void iter_dequeue(struct lanai_dev *lanai, vci_t vci)
1748 struct lanai_vcc *lvcc = lanai->vccs[vci];
1752 __clear_bit(vci, lanai->backlog_vccs);
1756 lvcc->tx.unqueue(lanai, lvcc, endptr);
1762 struct lanai_dev *lanai = from_timer(lanai, t, timer);
1766 if (lanai->conf1 & CONFIG1_POWERDOWN)
1771 if (spin_trylock(&lanai->servicelock)) {
1772 run_service(lanai);
1773 spin_unlock(&lanai->servicelock);
1778 vci_bitfield_iterate(lanai, lanai->backlog_vccs, iter_dequeue);
1782 get_statistics(lanai);
1784 mod_timer(&lanai->timer, jiffies + LANAI_POLL_PERIOD);
1787 static inline void lanai_timed_poll_start(struct lanai_dev *lanai)
1789 timer_setup(&lanai->timer, lanai_timed_poll, 0);
1790 lanai->timer.expires = jiffies + LANAI_POLL_PERIOD;
1791 add_timer(&lanai->timer);
1794 static inline void lanai_timed_poll_stop(struct lanai_dev *lanai)
1796 del_timer_sync(&lanai->timer);
1801 static inline void lanai_int_1(struct lanai_dev *lanai, u32 reason)
1806 spin_lock(&lanai->servicelock);
1807 run_service(lanai);
1808 spin_unlock(&lanai->servicelock);
1812 vcc_rx_aal0(lanai);
1819 get_statistics(lanai);
1823 lanai_check_status(lanai);
1828 lanai->number, (unsigned int) (reason & INT_DMASHUT),
1829 (unsigned int) reg_read(lanai, DMA_Addr_Reg));
1831 lanai_reset(lanai);
1836 lanai->number);
1837 conf1_write(lanai);
1838 lanai->stats.dma_reenable++;
1839 pcistatus_check(lanai, 0);
1844 lanai->number);
1845 pcistatus_check(lanai, 0);
1849 "segmentation shutdown, reason=0x%08X\n", lanai->number,
1851 lanai_reset(lanai);
1857 lanai->number,
1859 lanai_reset(lanai);
1871 reg_write(lanai, ack, IntAck_Reg);
1876 struct lanai_dev *lanai = devid;
1885 if (unlikely(lanai->conf1 & CONFIG1_POWERDOWN))
1889 reason = intr_pending(lanai);
1896 lanai_int_1(lanai, reason);
1897 reason = intr_pending(lanai);
1931 static int lanai_pci_start(struct lanai_dev *lanai)
1933 struct pci_dev *pci = lanai->pci;
1938 "PCI device", lanai->number);
1944 "(itf %d): No suitable DMA available.\n", lanai->number);
1950 /* Set latency timer to zero as per lanai docs */
1954 "PCI_LATENCY_TIMER: %d\n", lanai->number, result);
1957 pcistatus_check(lanai, 1);
1958 pcistatus_check(lanai, 0);
1970 static inline int vci0_is_ok(struct lanai_dev *lanai,
1976 if (lanai->naal0 != 0)
1978 lanai->conf2 |= CONFIG2_VCI0_NORMAL;
1979 conf2_write_if_powerup(lanai);
1987 static int vci_is_ok(struct lanai_dev *lanai, vci_t vci,
1991 const struct lanai_vcc *lvcc = lanai->vccs[vci];
1992 if (vci == 0 && !vci0_is_ok(lanai, qos))
2002 lanai->cbrvcc != NULL && lanai->cbrvcc != atmvcc)
2005 if (qos->aal == ATM_AAL0 && lanai->naal0 == 0 &&
2007 const struct lanai_vcc *vci0 = lanai->vccs[0];
2010 lanai->conf2 &= ~CONFIG2_VCI0_NORMAL;
2011 conf2_write_if_powerup(lanai);
2016 static int lanai_normalize_ci(struct lanai_dev *lanai,
2030 for (*vcip = ATM_NOT_RSV_VCI; *vcip < lanai->num_vci;
2032 if (vci_is_ok(lanai, *vcip, atmvcc))
2036 if (*vcip >= lanai->num_vci || *vcip < 0 ||
2037 !vci_is_ok(lanai, *vcip, atmvcc))
2090 static inline void lanai_cbr_setup(struct lanai_dev *lanai)
2092 reg_write(lanai, pcr_to_cbricg(&lanai->cbrvcc->qos), CBR_ICG_Reg);
2093 reg_write(lanai, lanai->cbrvcc->vci, CBR_PTR_Reg);
2094 lanai->conf2 |= CONFIG2_CBR_ENABLE;
2095 conf2_write(lanai);
2098 static inline void lanai_cbr_shutdown(struct lanai_dev *lanai)
2100 lanai->conf2 &= ~CONFIG2_CBR_ENABLE;
2101 conf2_write(lanai);
2109 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2115 lanai->number = atmdev->number;
2116 lanai->num_vci = NUM_VCI;
2117 bitmap_zero(lanai->backlog_vccs, NUM_VCI);
2118 bitmap_zero(lanai->transmit_ready, NUM_VCI);
2119 lanai->naal0 = 0;
2121 lanai->nbound = 0;
2123 lanai->cbrvcc = NULL;
2124 memset(&lanai->stats, 0, sizeof lanai->stats);
2125 spin_lock_init(&lanai->endtxlock);
2126 spin_lock_init(&lanai->servicelock);
2129 while (1 << atmdev->ci_range.vci_bits < lanai->num_vci)
2134 if ((result = lanai_pci_start(lanai)) != 0)
2136 raw_base = lanai->pci->resource[0].start;
2137 lanai->base = (bus_addr_t) ioremap(raw_base, LANAI_MAPPING_SIZE);
2138 if (lanai->base == NULL) {
2143 /* 3.3: Reset lanai and PHY */
2144 reset_board(lanai);
2145 lanai->conf1 = reg_read(lanai, Config1_Reg);
2146 lanai->conf1 &= ~(CONFIG1_GPOUT1 | CONFIG1_POWERDOWN |
2148 lanai->conf1 |= CONFIG1_SET_LEDMODE(LEDMODE_NOT_SOOL);
2149 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
2151 conf1_write(lanai);
2163 reg_read(lanai, Reset_Reg), &lanai->board_rev);
2168 if ((result = eeprom_read(lanai)) != 0)
2170 if ((result = eeprom_validate(lanai)) != 0)
2174 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
2176 conf1_write(lanai);
2178 lanai->conf1 |= (CONFIG1_GPOUT2 | CONFIG1_GPOUT3 | CONFIG1_DMA_ENABLE);
2179 conf1_write(lanai);
2182 if ((result = sram_test_and_clear(lanai)) != 0)
2185 /* 3.10: initialize lanai registers */
2186 lanai->conf1 |= CONFIG1_DMA_ENABLE;
2187 conf1_write(lanai);
2188 if ((result = service_buffer_allocate(lanai)) != 0)
2190 if ((result = vcc_table_allocate(lanai)) != 0)
2192 lanai->conf2 = (lanai->num_vci >= 512 ? CONFIG2_HOWMANY : 0) |
2194 conf2_write(lanai);
2195 reg_write(lanai, TX_FIFO_DEPTH, TxDepth_Reg);
2196 reg_write(lanai, 0, CBR_ICG_Reg); /* CBR defaults to no limit */
2197 if ((result = request_irq(lanai->pci->irq, lanai_int, IRQF_SHARED,
2198 DEV_LABEL, lanai)) != 0) {
2203 intr_enable(lanai, INT_ALL & ~(INT_PING | INT_WAKE));
2205 lanai->conf1 = (lanai->conf1 & ~CONFIG1_MASK_LOOPMODE) |
2208 conf1_write(lanai);
2209 lanai->status = reg_read(lanai, Status_Reg);
2212 lanai->conf1 |= CONFIG1_POWERDOWN;
2213 conf1_write(lanai);
2215 memcpy(atmdev->esi, eeprom_mac(lanai), ESI_LEN);
2216 lanai_timed_poll_start(lanai);
2218 "(%pMF)\n", lanai->number, (int) lanai->pci->revision,
2219 lanai->base, lanai->pci->irq, atmdev->esi);
2221 "board_rev=%d\n", lanai->number,
2222 lanai->type==lanai2 ? "2" : "HB", (unsigned int) lanai->serialno,
2223 (unsigned int) lanai->serialno, lanai->board_rev);
2227 vcc_table_deallocate(lanai);
2229 service_buffer_deallocate(lanai);
2231 reset_board(lanai);
2233 lanai->conf1 = reg_read(lanai, Config1_Reg) | CONFIG1_POWERDOWN;
2234 conf1_write(lanai);
2236 iounmap(lanai->base);
2237 lanai->base = NULL;
2239 pci_disable_device(lanai->pci);
2249 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2250 if (lanai->base==NULL)
2253 lanai->number);
2254 lanai_timed_poll_stop(lanai);
2256 lanai->conf1 = reg_read(lanai, Config1_Reg) & ~CONFIG1_POWERDOWN;
2257 conf1_write(lanai);
2259 intr_disable(lanai, INT_ALL);
2260 free_irq(lanai->pci->irq, lanai);
2261 reset_board(lanai);
2263 lanai->conf1 |= CONFIG1_POWERDOWN;
2264 conf1_write(lanai);
2266 pci_disable_device(lanai->pci);
2267 vcc_table_deallocate(lanai);
2268 service_buffer_deallocate(lanai);
2269 iounmap(lanai->base);
2270 kfree(lanai);
2277 struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2285 if (--lanai->naal0 <= 0)
2286 aal0_buffer_free(lanai);
2288 lanai_buf_deallocate(&lvcc->rx.buf, lanai->pci);
2292 if (atmvcc == lanai->cbrvcc) {
2294 lanai_cbr_shutdown(lanai);
2295 lanai->cbrvcc = NULL;
2297 lanai_shutdown_tx_vci(lanai, lvcc);
2298 lanai_buf_deallocate(&lvcc->tx.buf, lanai->pci);
2302 host_vcc_unbind(lanai, lvcc);
2312 struct lanai_dev *lanai;
2321 lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2322 result = lanai_normalize_ci(lanai, atmvcc, &vpi, &vci);
2328 DPRINTK(DEV_LABEL "(itf %d): open %d.%d\n", lanai->number,
2330 lvcc = lanai->vccs[vci];
2342 if (lanai->naal0 == 0)
2343 result = aal0_buffer_allocate(lanai);
2346 lanai, lvcc, &atmvcc->qos);
2356 lanai->naal0++;
2361 result = lanai_setup_tx_vci(lanai, lvcc, &atmvcc->qos);
2366 APRINTK(lanai->cbrvcc == NULL,
2368 lanai->cbrvcc = atmvcc;
2371 host_vcc_bind(lanai, lvcc, vci);
2381 if (lanai->cbrvcc == atmvcc)
2382 lanai_cbr_setup(lanai);
2395 struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2405 if (unlikely(lanai == NULL)) {
2406 DPRINTK("lanai_send: lanai==NULL for vci=%d\n", atmvcc->vci);
2414 vcc_tx_aal5(lanai, lvcc, skb);
2423 vcc_tx_aal0(lanai, lvcc, skb);
2445 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2451 atmdev->number, lanai->type==lanai2 ? "2" : "HB",
2452 (unsigned int) lanai->serialno,
2453 (unsigned int) lanai->magicno, lanai->num_vci);
2456 lanai->board_rev, (int) lanai->pci->revision);
2459 &lanai->eeprom[EEPROM_MAC]);
2462 "GPIN=%d\n", (lanai->status & STATUS_SOOL) ? 1 : 0,
2463 (lanai->status & STATUS_LOCD) ? 1 : 0,
2464 (lanai->status & STATUS_LED) ? 1 : 0,
2465 (lanai->status & STATUS_GPIN) ? 1 : 0);
2468 "aal0_rx=%zu\n", lanai_buf_size(&lanai->service),
2469 lanai->naal0 ? lanai_buf_size(&lanai->aal0buf) : 0);
2471 get_statistics(lanai);
2474 lanai->stats.ovfl_trash, lanai->stats.vci_trash,
2475 lanai->stats.hec_err, lanai->stats.atm_ovfl);
2480 lanai->stats.pcierr_parity_detect,
2481 lanai->stats.pcierr_serr_set,
2482 lanai->stats.pcierr_m_target_abort);
2485 "master_parity=%u\n", lanai->stats.pcierr_s_target_abort,
2486 lanai->stats.pcierr_master_parity);
2489 "no_rx=%u, bad_rx_aal=%u\n", lanai->stats.service_norx,
2490 lanai->stats.service_notx,
2491 lanai->stats.service_rxnotaal5);
2494 lanai->stats.dma_reenable, lanai->stats.card_reset);
2502 if ((lvcc = lanai->vccs[left]) != NULL)
2527 lvcc->tx.atmvcc == lanai->cbrvcc ? 'C' : 'U',
2555 struct lanai_dev *lanai;
2559 lanai = kzalloc(sizeof(*lanai), GFP_KERNEL);
2560 if (lanai == NULL) {
2570 kfree(lanai);
2574 atmdev->dev_data = lanai;
2575 lanai->pci = pci;
2576 lanai->type = (enum lanai_type) ident->device;
2582 kfree(lanai);