Lines Matching refs:iadev
74 static void desc_dbg(IADEV *iadev);
577 IADEV *iadev;
581 iadev = INPH_IA_DEV(vcc->dev);
582 iadev->NumEnabledCBR--;
583 SchedTbl = (u16*)(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize);
584 if (iadev->NumEnabledCBR == 0) {
585 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
589 for (i=0; i < iadev->CbrTotEntries; i++)
592 iadev->CbrRemEntries++;
601 static int ia_avail_descs(IADEV *iadev) {
603 ia_hack_tcq(iadev);
604 if (iadev->host_tcq_wr >= iadev->ffL.tcq_rd)
605 tmp = (iadev->host_tcq_wr - iadev->ffL.tcq_rd) / 2;
607 tmp = (iadev->ffL.tcq_ed - iadev->ffL.tcq_rd + 2 + iadev->host_tcq_wr -
608 iadev->ffL.tcq_st) / 2;
614 static int ia_que_tx (IADEV *iadev) {
618 num_desc = ia_avail_descs(iadev);
620 while (num_desc && (skb = skb_dequeue(&iadev->tx_backlog))) {
632 skb_queue_head(&iadev->tx_backlog, skb);
639 static void ia_tx_poll (IADEV *iadev) {
645 ia_hack_tcq(iadev);
646 while ( (rtne = ia_deque_rtn_q(&iadev->tx_return_q))) {
684 ia_enque_head_rtn_q (&iadev->tx_return_q, rtne);
696 ia_que_tx(iadev);
701 static void ia_eeprom_put (IADEV *iadev, u32 addr, u_short val)
723 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS);
725 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS);
737 static u16 ia_eeprom_get (IADEV *iadev, u32 addr)
761 static void ia_hw_type(IADEV *iadev) {
762 u_short memType = ia_eeprom_get(iadev, 25);
763 iadev->memType = memType;
765 iadev->num_tx_desc = IA_TX_BUF;
766 iadev->tx_buf_sz = IA_TX_BUF_SZ;
767 iadev->num_rx_desc = IA_RX_BUF;
768 iadev->rx_buf_sz = IA_RX_BUF_SZ;
771 iadev->num_tx_desc = IA_TX_BUF / 2;
773 iadev->num_tx_desc = IA_TX_BUF;
774 iadev->tx_buf_sz = IA_TX_BUF_SZ;
776 iadev->num_rx_desc = IA_RX_BUF / 2;
778 iadev->num_rx_desc = IA_RX_BUF;
779 iadev->rx_buf_sz = IA_RX_BUF_SZ;
783 iadev->num_tx_desc = IA_TX_BUF / 8;
785 iadev->num_tx_desc = IA_TX_BUF;
786 iadev->tx_buf_sz = IA_TX_BUF_SZ;
788 iadev->num_rx_desc = IA_RX_BUF / 8;
790 iadev->num_rx_desc = IA_RX_BUF;
791 iadev->rx_buf_sz = IA_RX_BUF_SZ;
793 iadev->rx_pkt_ram = TX_PACKET_RAM + (iadev->num_tx_desc * iadev->tx_buf_sz);
795 iadev->num_tx_desc, iadev->tx_buf_sz, iadev->num_rx_desc,
796 iadev->rx_buf_sz, iadev->rx_pkt_ram);)
800 iadev->phy_type = PHY_OC3C_S;
802 iadev->phy_type = PHY_UTP155;
804 iadev->phy_type = PHY_OC3C_M;
807 iadev->phy_type = memType & FE_MASK;
808 IF_INIT(printk("memType = 0x%x iadev->phy_type = 0x%x\n",
809 memType,iadev->phy_type);)
810 if (iadev->phy_type == FE_25MBIT_PHY)
811 iadev->LineRate = (u32)(((25600000/8)*26)/(27*53));
812 else if (iadev->phy_type == FE_DS3_PHY)
813 iadev->LineRate = (u32)(((44736000/8)*26)/(27*53));
814 else if (iadev->phy_type == FE_E3_PHY)
815 iadev->LineRate = (u32)(((34368000/8)*26)/(27*53));
817 iadev->LineRate = (u32)(ATM_OC3_PCR);
818 IF_INIT(printk("iadev->LineRate = %d \n", iadev->LineRate);)
832 static void ia_frontend_intr(struct iadev_priv *iadev)
836 if (iadev->phy_type & FE_25MBIT_PHY) {
837 status = ia_phy_read32(iadev, MB25_INTR_STATUS);
838 iadev->carrier_detect = (status & MB25_IS_GSB) ? 1 : 0;
839 } else if (iadev->phy_type & FE_DS3_PHY) {
840 ia_phy_read32(iadev, SUNI_DS3_FRM_INTR_STAT);
841 status = ia_phy_read32(iadev, SUNI_DS3_FRM_STAT);
842 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
843 } else if (iadev->phy_type & FE_E3_PHY) {
844 ia_phy_read32(iadev, SUNI_E3_FRM_MAINT_INTR_IND);
845 status = ia_phy_read32(iadev, SUNI_E3_FRM_FRAM_INTR_IND_STAT);
846 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
848 status = ia_phy_read32(iadev, SUNI_RSOP_STATUS);
849 iadev->carrier_detect = (status & SUNI_LOSV) ? 0 : 1;
853 iadev->carrier_detect ? "detected" : "lost signal");
856 static void ia_mb25_init(struct iadev_priv *iadev)
861 ia_phy_write32(iadev, MB25_MASTER_CTRL, MB25_MC_DRIC | MB25_MC_DREC);
862 ia_phy_write32(iadev, MB25_DIAG_CONTROL, 0);
864 iadev->carrier_detect =
865 (ia_phy_read32(iadev, MB25_INTR_STATUS) & MB25_IS_GSB) ? 1 : 0;
873 static void ia_phy_write(struct iadev_priv *iadev,
877 ia_phy_write32(iadev, regs->reg, regs->val);
882 static void ia_suni_pm7345_init_ds3(struct iadev_priv *iadev)
894 status = ia_phy_read32(iadev, SUNI_DS3_FRM_STAT);
895 iadev->carrier_detect = (status & SUNI_DS3_LOSV) ? 0 : 1;
897 ia_phy_write(iadev, suni_ds3_init, ARRAY_SIZE(suni_ds3_init));
900 static void ia_suni_pm7345_init_e3(struct iadev_priv *iadev)
915 status = ia_phy_read32(iadev, SUNI_E3_FRM_FRAM_INTR_IND_STAT);
916 iadev->carrier_detect = (status & SUNI_E3_LOS) ? 0 : 1;
917 ia_phy_write(iadev, suni_e3_init, ARRAY_SIZE(suni_e3_init));
920 static void ia_suni_pm7345_init(struct iadev_priv *iadev)
958 if (iadev->phy_type & FE_DS3_PHY)
959 ia_suni_pm7345_init_ds3(iadev);
961 ia_suni_pm7345_init_e3(iadev);
963 ia_phy_write(iadev, suni_init, ARRAY_SIZE(suni_init));
965 ia_phy_write32(iadev, SUNI_CONFIG, ia_phy_read32(iadev, SUNI_CONFIG) &
1016 RAM_BASE*((iadev->mem)/(128 * 1024))
1018 IPHASE5575_FRAG_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024))
1020 IPHASE5575_REASS_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024))
1025 static void desc_dbg(IADEV *iadev) {
1031 tcq_wr_ptr = readw(iadev->seg_reg+TCQ_WR_PTR);
1033 tcq_wr_ptr, readw(iadev->seg_ram+tcq_wr_ptr),
1034 readw(iadev->seg_ram+tcq_wr_ptr-2));
1035 printk(" host_tcq_wr = 0x%x host_tcq_rd = 0x%x \n", iadev->host_tcq_wr,
1036 iadev->ffL.tcq_rd);
1037 tcq_st_ptr = readw(iadev->seg_reg+TCQ_ST_ADR);
1038 tcq_ed_ptr = readw(iadev->seg_reg+TCQ_ED_ADR);
1042 tmp = iadev->seg_ram+tcq_st_ptr;
1046 for(i=0; i <iadev->num_tx_desc; i++)
1047 printk("Desc_tbl[%d] = %d \n", i, iadev->desc_tbl[i].timestamp);
1056 IADEV *iadev;
1061 iadev = INPH_IA_DEV(dev);
1062 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1065 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_RD_PTR) & 0xffff;
1067 if (excpq_rd_ptr == *(u16*)(iadev->reass_reg + EXCP_Q_WR_PTR))
1070 vci = readw(iadev->reass_ram+excpq_rd_ptr);
1071 error = readw(iadev->reass_ram+excpq_rd_ptr+2) & 0x0007;
1074 if (excpq_rd_ptr > (readw(iadev->reass_reg + EXCP_Q_ED_ADR)& 0xffff))
1075 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_ST_ADR)& 0xffff;
1076 writew( excpq_rd_ptr, iadev->reass_reg + EXCP_Q_RD_PTR);
1077 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1084 IADEV *iadev;
1085 iadev = INPH_IA_DEV(dev);
1086 writew(desc, iadev->reass_ram+iadev->rfL.fdq_wr);
1087 iadev->rfL.fdq_wr +=2;
1088 if (iadev->rfL.fdq_wr > iadev->rfL.fdq_ed)
1089 iadev->rfL.fdq_wr = iadev->rfL.fdq_st;
1090 writew(iadev->rfL.fdq_wr, iadev->reass_reg+FREEQ_WR_PTR);
1096 IADEV *iadev;
1106 iadev = INPH_IA_DEV(dev);
1107 if (iadev->rfL.pcq_rd == (readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff))
1113 desc = readw(iadev->reass_ram+iadev->rfL.pcq_rd) & 0x1fff;
1114 IF_RX(printk("reass_ram = %p iadev->rfL.pcq_rd = 0x%x desc = %d\n",
1115 iadev->reass_ram, iadev->rfL.pcq_rd, desc);
1117 readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff);)
1119 if ( iadev->rfL.pcq_rd== iadev->rfL.pcq_ed)
1120 iadev->rfL.pcq_rd = iadev->rfL.pcq_st;
1122 iadev->rfL.pcq_rd += 2;
1123 writew(iadev->rfL.pcq_rd, iadev->reass_reg+PCQ_RD_PTR);
1128 buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
1131 if (!desc || (desc > iadev->num_rx_desc) ||
1132 ((buf_desc_ptr->vc_index & 0xffff) >= iadev->num_vc)) {
1137 vcc = iadev->rx_open[buf_desc_ptr->vc_index & 0xffff];
1171 if (len > iadev->rx_buf_sz) {
1172 printk("Over %d bytes sdu received, dropped!!!\n", iadev->rx_buf_sz);
1186 skb_queue_tail(&iadev->rx_dma_q, skb);
1189 wr_ptr = iadev->rx_dle_q.write;
1190 wr_ptr->sys_pkt_addr = dma_map_single(&iadev->pci->dev, skb->data,
1197 if(++wr_ptr == iadev->rx_dle_q.end)
1198 wr_ptr = iadev->rx_dle_q.start;
1199 iadev->rx_dle_q.write = wr_ptr;
1202 writel(1, iadev->dma+IPHASE5575_RX_COUNTER);
1211 IADEV *iadev;
1215 iadev = INPH_IA_DEV(dev);
1216 status = readl(iadev->reass_reg+REASS_INTR_STATUS_REG) & 0xffff;
1226 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1231 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1233 iadev->rxing = 1;
1237 if (iadev->rxing) {
1238 iadev->rx_tmp_cnt = iadev->rx_pkt_cnt;
1239 iadev->rx_tmp_jif = jiffies;
1240 iadev->rxing = 0;
1242 else if ((time_after(jiffies, iadev->rx_tmp_jif + 50)) &&
1243 ((iadev->rx_pkt_cnt - iadev->rx_tmp_cnt) == 0)) {
1244 for (i = 1; i <= iadev->num_rx_desc; i++)
1247 writew( ~(RX_FREEQ_EMPT|RX_EXCP_RCVD),iadev->reass_reg+REASS_MASK_REG);
1248 iadev->rxing = 1;
1273 IADEV *iadev;
1281 iadev = INPH_IA_DEV(dev);
1288 dle = iadev->rx_dle_q.read;
1289 dle_lp = readl(iadev->dma+IPHASE5575_RX_LIST_ADDR) & (sizeof(struct dle)*DLE_ENTRIES - 1);
1290 cur_dle = (struct dle*)(iadev->rx_dle_q.start + (dle_lp >> 4));
1294 skb = skb_dequeue(&iadev->rx_dma_q);
1311 dma_unmap_single(&iadev->pci->dev, iadev->rx_dle_q.write->sys_pkt_addr,
1332 if ((length > iadev->rx_buf_sz) || (length >
1352 iadev->rx_pkt_cnt++;
1355 if (++dle == iadev->rx_dle_q.end)
1356 dle = iadev->rx_dle_q.start;
1358 iadev->rx_dle_q.read = dle;
1362 if (!iadev->rxing) {
1363 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1365 state = readl(iadev->reass_reg + REASS_MASK_REG) & 0xffff;
1367 iadev->reass_reg+REASS_MASK_REG);
1368 iadev->rxing++;
1376 IADEV *iadev;
1379 IF_EVENT(printk("iadev: open_rx %d.%d\n", vcc->vpi, vcc->vci);)
1382 iadev = INPH_IA_DEV(vcc->dev);
1384 if (iadev->phy_type & FE_25MBIT_PHY) {
1391 vc_table = iadev->reass_ram+RX_VC_TABLE*iadev->memSize;
1402 init_abr_vc(iadev, &srv_p);
1403 ia_open_abr_vc(iadev, &srv_p, vcc, 0);
1406 reass_ptr = iadev->reass_ram+REASS_TABLE*iadev->memSize;
1411 if (iadev->rx_open[vcc->vci])
1414 iadev->rx_open[vcc->vci] = vcc;
1420 IADEV *iadev;
1431 iadev = INPH_IA_DEV(dev);
1432 // spin_lock_init(&iadev->rx_lock);
1435 dle_addr = dma_alloc_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE,
1436 &iadev->rx_dle_dma, GFP_KERNEL);
1441 iadev->rx_dle_q.start = (struct dle *)dle_addr;
1442 iadev->rx_dle_q.read = iadev->rx_dle_q.start;
1443 iadev->rx_dle_q.write = iadev->rx_dle_q.start;
1444 iadev->rx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
1450 writel(iadev->rx_dle_dma & 0xfffff000,
1451 iadev->dma + IPHASE5575_RX_LIST_ADDR);
1453 iadev->dma+IPHASE5575_TX_LIST_ADDR,
1454 readl(iadev->dma + IPHASE5575_TX_LIST_ADDR));
1456 iadev->dma+IPHASE5575_RX_LIST_ADDR,
1457 readl(iadev->dma + IPHASE5575_RX_LIST_ADDR));)
1459 writew(0xffff, iadev->reass_reg+REASS_MASK_REG);
1460 writew(0, iadev->reass_reg+MODE_REG);
1461 writew(RESET_REASS, iadev->reass_reg+REASS_COMMAND_REG);
1477 writew(RX_DESC_BASE >> 16, iadev->reass_reg+REASS_DESC_BASE);
1479 writew(iadev->rx_buf_sz, iadev->reass_reg+BUF_SIZE);
1482 iadev->RX_DESC_BASE_ADDR = iadev->reass_ram+RX_DESC_BASE*iadev->memSize;
1483 buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
1486 rx_pkt_start = iadev->rx_pkt_ram;
1487 for(i=1; i<=iadev->num_rx_desc; i++)
1493 rx_pkt_start += iadev->rx_buf_sz;
1496 i = FREE_BUF_DESC_Q*iadev->memSize;
1497 writew(i >> 16, iadev->reass_reg+REASS_QUEUE_BASE);
1498 writew(i, iadev->reass_reg+FREEQ_ST_ADR);
1499 writew(i+iadev->num_rx_desc*sizeof(u_short),
1500 iadev->reass_reg+FREEQ_ED_ADR);
1501 writew(i, iadev->reass_reg+FREEQ_RD_PTR);
1502 writew(i+iadev->num_rx_desc*sizeof(u_short),
1503 iadev->reass_reg+FREEQ_WR_PTR);
1505 freeq_st_adr = readw(iadev->reass_reg+FREEQ_ST_ADR);
1506 freeq_start = (u_short *)(iadev->reass_ram+freeq_st_adr);
1507 for(i=1; i<=iadev->num_rx_desc; i++)
1514 i = (PKT_COMP_Q * iadev->memSize) & 0xffff;
1515 writew(i, iadev->reass_reg+PCQ_ST_ADR);
1516 writew(i+iadev->num_vc*sizeof(u_short), iadev->reass_reg+PCQ_ED_ADR);
1517 writew(i, iadev->reass_reg+PCQ_RD_PTR);
1518 writew(i, iadev->reass_reg+PCQ_WR_PTR);
1521 i = (EXCEPTION_Q * iadev->memSize) & 0xffff;
1522 writew(i, iadev->reass_reg+EXCP_Q_ST_ADR);
1524 iadev->reass_reg+EXCP_Q_ED_ADR);
1525 writew(i, iadev->reass_reg+EXCP_Q_RD_PTR);
1526 writew(i, iadev->reass_reg+EXCP_Q_WR_PTR);
1529 iadev->rfL.fdq_st = readw(iadev->reass_reg+FREEQ_ST_ADR) & 0xffff;
1530 iadev->rfL.fdq_ed = readw(iadev->reass_reg+FREEQ_ED_ADR) & 0xffff ;
1531 iadev->rfL.fdq_rd = readw(iadev->reass_reg+FREEQ_RD_PTR) & 0xffff;
1532 iadev->rfL.fdq_wr = readw(iadev->reass_reg+FREEQ_WR_PTR) & 0xffff;
1533 iadev->rfL.pcq_st = readw(iadev->reass_reg+PCQ_ST_ADR) & 0xffff;
1534 iadev->rfL.pcq_ed = readw(iadev->reass_reg+PCQ_ED_ADR) & 0xffff;
1535 iadev->rfL.pcq_rd = readw(iadev->reass_reg+PCQ_RD_PTR) & 0xffff;
1536 iadev->rfL.pcq_wr = readw(iadev->reass_reg+PCQ_WR_PTR) & 0xffff;
1539 iadev->rfL.pcq_st, iadev->rfL.pcq_ed, iadev->rfL.pcq_rd,
1540 iadev->rfL.pcq_wr);)
1543 /* writew(0x0b80, iadev->reass_reg+VP_LKUP_BASE); */
1550 i = REASS_TABLE * iadev->memSize;
1551 writew((i >> 3), iadev->reass_reg+REASS_TABLE_BASE);
1553 reass_table = (u16 *)(iadev->reass_ram+i);
1554 j = REASS_TABLE_SZ * iadev->memSize;
1559 while (i != iadev->num_vc) {
1563 i = RX_VC_TABLE * iadev->memSize;
1564 writew(((i>>3) & 0xfff8) | vcsize_sel, iadev->reass_reg+VC_LKUP_BASE);
1565 vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);
1566 j = RX_VC_TABLE_SZ * iadev->memSize;
1578 i = ABR_VC_TABLE * iadev->memSize;
1579 writew(i >> 3, iadev->reass_reg+ABR_LKUP_BASE);
1581 i = ABR_VC_TABLE * iadev->memSize;
1582 abr_vc_table = (struct abr_vc_table *)(iadev->reass_ram+i);
1583 j = REASS_TABLE_SZ * iadev->memSize;
1594 writew(0xff00, iadev->reass_reg+VP_FILTER);
1595 writew(0, iadev->reass_reg+XTRA_RM_OFFSET);
1596 writew(0x1, iadev->reass_reg+PROTOCOL_ID);
1602 writew(0xF6F8, iadev->reass_reg+PKT_TM_CNT );
1607 writew(i, iadev->reass_reg+TMOUT_RANGE);
1610 for(i=0; i<iadev->num_tx_desc;i++)
1611 iadev->desc_tbl[i].timestamp = 0;
1614 readw(iadev->reass_reg+REASS_INTR_STATUS_REG);
1617 writew(~(RX_FREEQ_EMPT|RX_PKT_RCVD), iadev->reass_reg+REASS_MASK_REG);
1619 skb_queue_head_init(&iadev->rx_dma_q);
1620 iadev->rx_free_desc_qhead = NULL;
1622 iadev->rx_open = kcalloc(iadev->num_vc, sizeof(void *), GFP_KERNEL);
1623 if (!iadev->rx_open) {
1629 iadev->rxing = 1;
1630 iadev->rx_pkt_cnt = 0;
1632 writew(R_ONLINE, iadev->reass_reg+MODE_REG);
1636 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,
1637 iadev->rx_dle_dma);
1660 IADEV *iadev;
1664 iadev = INPH_IA_DEV(dev);
1666 status = readl(iadev->seg_reg+SEG_INTR_STATUS_REG);
1670 spin_lock_irqsave(&iadev->tx_lock, flags);
1671 ia_tx_poll(iadev);
1672 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1673 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
1674 if (iadev->close_pending)
1675 wake_up(&iadev->close_wait);
1685 IADEV *iadev;
1693 iadev = INPH_IA_DEV(dev);
1694 spin_lock_irqsave(&iadev->tx_lock, flags);
1695 dle = iadev->tx_dle_q.read;
1696 dle_lp = readl(iadev->dma+IPHASE5575_TX_LIST_ADDR) &
1698 cur_dle = (struct dle*)(iadev->tx_dle_q.start + (dle_lp >> 4));
1702 skb = skb_dequeue(&iadev->tx_dma_q);
1706 if (!((dle - iadev->tx_dle_q.start)%(2*sizeof(struct dle)))) {
1707 dma_unmap_single(&iadev->pci->dev, dle->sys_pkt_addr, skb->len,
1713 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1721 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1725 if (vcc->qos.txtp.pcr >= iadev->rate_limit) {
1739 if (++dle == iadev->tx_dle_q.end)
1740 dle = iadev->tx_dle_q.start;
1742 iadev->tx_dle_q.read = dle;
1743 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1749 IADEV *iadev;
1753 IF_EVENT(printk("iadev: open_tx entered vcc->vci = %d\n", vcc->vci);)
1755 iadev = INPH_IA_DEV(vcc->dev);
1757 if (iadev->phy_type & FE_25MBIT_PHY) {
1770 (iadev->tx_buf_sz - sizeof(struct cpcs_trailer))){
1772 vcc->qos.txtp.max_sdu,iadev->tx_buf_sz);
1782 vcc->qos.txtp.pcr = iadev->LineRate;
1784 vcc->qos.txtp.pcr = iadev->LineRate;
1787 if (vcc->qos.txtp.pcr > iadev->LineRate)
1788 vcc->qos.txtp.pcr = iadev->LineRate;
1791 if (ia_vcc->pcr > (iadev->LineRate / 6) ) ia_vcc->ltimeout = HZ / 10;
1792 else if (ia_vcc->pcr > (iadev->LineRate / 130)) ia_vcc->ltimeout = HZ;
1795 if (ia_vcc->pcr < iadev->rate_limit)
1797 if (ia_vcc->pcr < iadev->rate_limit) {
1812 vc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR;
1813 evc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR;
1832 vc->acr = cellrate_to_float(iadev->LineRate);
1841 init_abr_vc(iadev, &srv_p);
1845 int tmpsum = iadev->sum_mcr+iadev->sum_cbr+vcc->qos.txtp.min_pcr;
1846 if (tmpsum > iadev->LineRate)
1849 iadev->sum_mcr += vcc->qos.txtp.min_pcr;
1874 ia_open_abr_vc(iadev, &srv_p, vcc, 1);
1876 if (iadev->phy_type & FE_25MBIT_PHY) {
1880 if (vcc->qos.txtp.max_pcr > iadev->LineRate) {
1886 if ((ret = ia_cbr_setup (iadev, vcc)) < 0) {
1890 printk("iadev: Non UBR, ABR and CBR traffic not supported\n");
1893 iadev->testTable[vcc->vci]->vc_status |= VC_ACTIVE;
1901 IADEV *iadev;
1915 iadev = INPH_IA_DEV(dev);
1916 spin_lock_init(&iadev->tx_lock);
1919 readw(iadev->seg_reg+SEG_MASK_REG));)
1922 dle_addr = dma_alloc_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE,
1923 &iadev->tx_dle_dma, GFP_KERNEL);
1928 iadev->tx_dle_q.start = (struct dle*)dle_addr;
1929 iadev->tx_dle_q.read = iadev->tx_dle_q.start;
1930 iadev->tx_dle_q.write = iadev->tx_dle_q.start;
1931 iadev->tx_dle_q.end = (struct dle*)((unsigned long)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
1934 writel(iadev->tx_dle_dma & 0xfffff000,
1935 iadev->dma + IPHASE5575_TX_LIST_ADDR);
1936 writew(0xffff, iadev->seg_reg+SEG_MASK_REG);
1937 writew(0, iadev->seg_reg+MODE_REG_0);
1938 writew(RESET_SEG, iadev->seg_reg+SEG_COMMAND_REG);
1939 iadev->MAIN_VC_TABLE_ADDR = iadev->seg_ram+MAIN_VC_TABLE*iadev->memSize;
1940 iadev->EXT_VC_TABLE_ADDR = iadev->seg_ram+EXT_VC_TABLE*iadev->memSize;
1941 iadev->ABR_SCHED_TABLE_ADDR=iadev->seg_ram+ABR_SCHED_TABLE*iadev->memSize;
1963 writew(TX_DESC_BASE, iadev->seg_reg+SEG_DESC_BASE);
1966 buf_desc_ptr =(struct tx_buf_desc *)(iadev->seg_ram+TX_DESC_BASE);
1970 for(i=1; i<=iadev->num_tx_desc; i++)
1977 tx_pkt_start += iadev->tx_buf_sz;
1979 iadev->tx_buf = kmalloc_array(iadev->num_tx_desc,
1980 sizeof(*iadev->tx_buf),
1982 if (!iadev->tx_buf) {
1986 for (i= 0; i< iadev->num_tx_desc; i++)
1995 iadev->tx_buf[i].cpcs = cpcs;
1996 iadev->tx_buf[i].dma_addr = dma_map_single(&iadev->pci->dev,
2001 iadev->desc_tbl = kmalloc_array(iadev->num_tx_desc,
2002 sizeof(*iadev->desc_tbl),
2004 if (!iadev->desc_tbl) {
2010 i = TX_COMP_Q * iadev->memSize;
2011 writew(i >> 16, iadev->seg_reg+SEG_QUEUE_BASE);
2014 writew(i, iadev->seg_reg+TCQ_ST_ADR);
2015 writew(i, iadev->seg_reg+TCQ_RD_PTR);
2016 writew(i+iadev->num_tx_desc*sizeof(u_short),iadev->seg_reg+TCQ_WR_PTR);
2017 iadev->host_tcq_wr = i + iadev->num_tx_desc*sizeof(u_short);
2018 writew(i+2 * iadev->num_tx_desc * sizeof(u_short),
2019 iadev->seg_reg+TCQ_ED_ADR);
2021 tcq_st_adr = readw(iadev->seg_reg+TCQ_ST_ADR);
2022 tcq_start = (u_short *)(iadev->seg_ram+tcq_st_adr);
2023 for(i=1; i<=iadev->num_tx_desc; i++)
2030 i = PKT_RDY_Q * iadev->memSize;
2031 writew(i, iadev->seg_reg+PRQ_ST_ADR);
2032 writew(i+2 * iadev->num_tx_desc * sizeof(u_short),
2033 iadev->seg_reg+PRQ_ED_ADR);
2034 writew(i, iadev->seg_reg+PRQ_RD_PTR);
2035 writew(i, iadev->seg_reg+PRQ_WR_PTR);
2038 iadev->ffL.prq_st = readw(iadev->seg_reg+PRQ_ST_ADR) & 0xffff;
2039 iadev->ffL.prq_ed = readw(iadev->seg_reg+PRQ_ED_ADR) & 0xffff;
2040 iadev->ffL.prq_wr = readw(iadev->seg_reg+PRQ_WR_PTR) & 0xffff;
2042 iadev->ffL.tcq_st = readw(iadev->seg_reg+TCQ_ST_ADR) & 0xffff;
2043 iadev->ffL.tcq_ed = readw(iadev->seg_reg+TCQ_ED_ADR) & 0xffff;
2044 iadev->ffL.tcq_rd = readw(iadev->seg_reg+TCQ_RD_PTR) & 0xffff;
2048 prq_st_adr = readw(iadev->seg_reg+PRQ_ST_ADR);
2049 prq_start = (u_short *)(iadev->seg_ram+prq_st_adr);
2050 for(i=1; i<=iadev->num_tx_desc; i++)
2058 writew(0,iadev->seg_reg+CBR_PTR_BASE);
2060 tmp16 = (iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize)>>17;
2062 writew(tmp16,iadev->seg_reg+CBR_PTR_BASE);
2066 readw(iadev->seg_reg+CBR_PTR_BASE));)
2067 tmp16 = (CBR_SCHED_TABLE*iadev->memSize) >> 1;
2068 writew(tmp16, iadev->seg_reg+CBR_TAB_BEG);
2070 readw(iadev->seg_reg+CBR_TAB_BEG));)
2071 writew(tmp16, iadev->seg_reg+CBR_TAB_END+1); // CBR_PTR;
2072 tmp16 = (CBR_SCHED_TABLE*iadev->memSize + iadev->num_vc*6 - 2) >> 1;
2073 writew(tmp16, iadev->seg_reg+CBR_TAB_END);
2074 IF_INIT(printk("iadev->seg_reg = 0x%p CBR_PTR_BASE = 0x%x\n",
2075 iadev->seg_reg, readw(iadev->seg_reg+CBR_PTR_BASE));)
2077 readw(iadev->seg_reg+CBR_TAB_BEG), readw(iadev->seg_reg+CBR_TAB_END),
2078 readw(iadev->seg_reg+CBR_TAB_END+1));)
2081 memset_io(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize,
2082 0, iadev->num_vc*6);
2083 iadev->CbrRemEntries = iadev->CbrTotEntries = iadev->num_vc*3;
2084 iadev->CbrEntryPt = 0;
2085 iadev->Granularity = MAX_ATM_155 / iadev->CbrTotEntries;
2086 iadev->NumEnabledCBR = 0;
2099 while (i != iadev->num_vc) {
2104 i = MAIN_VC_TABLE * iadev->memSize;
2105 writew(vcsize_sel | ((i >> 8) & 0xfff8),iadev->seg_reg+VCT_BASE);
2106 i = EXT_VC_TABLE * iadev->memSize;
2107 writew((i >> 8) & 0xfffe, iadev->seg_reg+VCTE_BASE);
2108 i = UBR_SCHED_TABLE * iadev->memSize;
2109 writew((i & 0xffff) >> 11, iadev->seg_reg+UBR_SBPTR_BASE);
2110 i = UBR_WAIT_Q * iadev->memSize;
2111 writew((i >> 7) & 0xffff, iadev->seg_reg+UBRWQ_BASE);
2112 memset((caddr_t)(iadev->seg_ram+UBR_SCHED_TABLE*iadev->memSize),
2113 0, iadev->num_vc*8);
2122 i = ABR_SCHED_TABLE * iadev->memSize;
2123 writew((i >> 11) & 0xffff, iadev->seg_reg+ABR_SBPTR_BASE);
2124 i = ABR_WAIT_Q * iadev->memSize;
2125 writew((i >> 7) & 0xffff, iadev->seg_reg+ABRWQ_BASE);
2127 i = ABR_SCHED_TABLE*iadev->memSize;
2128 memset((caddr_t)(iadev->seg_ram+i), 0, iadev->num_vc*4);
2129 vc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR;
2130 evc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR;
2131 iadev->testTable = kmalloc_array(iadev->num_vc,
2132 sizeof(*iadev->testTable),
2134 if (!iadev->testTable) {
2138 for(i=0; i<iadev->num_vc; i++)
2142 iadev->testTable[i] = kmalloc(sizeof(struct testTable_t),
2144 if (!iadev->testTable[i])
2146 iadev->testTable[i]->lastTime = 0;
2147 iadev->testTable[i]->fract = 0;
2148 iadev->testTable[i]->vc_status = VC_UBR;
2156 if (iadev->phy_type & FE_25MBIT_PHY) {
2157 writew(RATE25, iadev->seg_reg+MAXRATE);
2158 writew((UBR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2161 writew(cellrate_to_float(iadev->LineRate),iadev->seg_reg+MAXRATE);
2162 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2165 writew(0, iadev->seg_reg+IDLEHEADHI);
2166 writew(0, iadev->seg_reg+IDLEHEADLO);
2169 writew(0xaa00, iadev->seg_reg+ABRUBR_ARB);
2171 iadev->close_pending = 0;
2172 init_waitqueue_head(&iadev->close_wait);
2173 init_waitqueue_head(&iadev->timeout_wait);
2174 skb_queue_head_init(&iadev->tx_dma_q);
2175 ia_init_rtn_q(&iadev->tx_return_q);
2178 writew(RM_TYPE_4_0, iadev->seg_reg+RM_TYPE);
2179 skb_queue_head_init (&iadev->tx_backlog);
2182 writew(MODE_REG_1_VAL, iadev->seg_reg+MODE_REG_1);
2185 writew(T_ONLINE, iadev->seg_reg+MODE_REG_0);
2188 readw(iadev->seg_reg+SEG_INTR_STATUS_REG);
2191 writew(~(TRANSMIT_DONE | TCQ_NOT_EMPTY), iadev->seg_reg+SEG_MASK_REG);
2192 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
2193 iadev->tx_pkt_cnt = 0;
2194 iadev->rate_limit = iadev->LineRate / 3;
2200 kfree(iadev->testTable[i]);
2201 kfree(iadev->testTable);
2203 kfree(iadev->desc_tbl);
2205 i = iadev->num_tx_desc;
2208 struct cpcs_trailer_desc *desc = iadev->tx_buf + i;
2210 dma_unmap_single(&iadev->pci->dev, desc->dma_addr,
2214 kfree(iadev->tx_buf);
2216 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,
2217 iadev->tx_dle_dma);
2225 IADEV *iadev;
2230 iadev = INPH_IA_DEV(dev);
2231 while( (status = readl(iadev->reg+IPHASE5575_BUS_STATUS_REG) & 0x7f))
2244 writel(STAT_DLERINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);
2255 writel(STAT_DLETINT, iadev->reg + IPHASE5575_BUS_STATUS_REG);
2261 ia_frontend_intr(iadev);
2272 IADEV *iadev;
2277 iadev = INPH_IA_DEV(dev);
2279 iadev->reg+IPHASE5575_MAC1)));
2280 mac2 = cpu_to_be16(le16_to_cpu(readl(iadev->reg+IPHASE5575_MAC2)));
2292 IADEV *iadev;
2296 iadev = INPH_IA_DEV(dev);
2298 error = pci_read_config_dword(iadev->pci, i * 4, &pci[i]);
2302 writel(0, iadev->reg+IPHASE5575_EXT_RESET);
2304 error = pci_write_config_dword(iadev->pci, i * 4, pci[i]);
2315 IADEV *iadev;
2329 iadev = INPH_IA_DEV(dev);
2330 real_base = pci_resource_start (iadev->pci, 0);
2331 iadev->irq = iadev->pci->irq;
2333 error = pci_read_config_word(iadev->pci, PCI_COMMAND, &command);
2340 dev->number, iadev->pci->revision, real_base, iadev->irq);)
2344 iadev->pci_map_size = pci_resource_len(iadev->pci, 0);
2346 if (iadev->pci_map_size == 0x100000){
2347 iadev->num_vc = 4096;
2349 iadev->memSize = 4;
2351 else if (iadev->pci_map_size == 0x40000) {
2352 iadev->num_vc = 1024;
2353 iadev->memSize = 1;
2356 printk("Unknown pci_map_size = 0x%x\n", iadev->pci_map_size);
2359 IF_INIT(printk (DEV_LABEL "map size: %i\n", iadev->pci_map_size);)
2362 pci_set_master(iadev->pci);
2370 base = ioremap(real_base,iadev->pci_map_size); /* ioremap is not resolved ??? */
2379 dev->number, iadev->pci->revision, base, iadev->irq);)
2382 iadev->mem = iadev->pci_map_size /2;
2383 iadev->real_base = real_base;
2384 iadev->base = base;
2387 iadev->reg = base + REG_BASE;
2389 iadev->seg_reg = base + SEG_BASE;
2391 iadev->reass_reg = base + REASS_BASE;
2393 iadev->phy = base + PHY_BASE;
2394 iadev->dma = base + PHY_BASE;
2396 iadev->ram = base + ACTUAL_RAM_BASE;
2397 iadev->seg_ram = base + ACTUAL_SEG_RAM_BASE;
2398 iadev->reass_ram = base + ACTUAL_REASS_RAM_BASE;
2402 iadev->reg,iadev->seg_reg,iadev->reass_reg,
2403 iadev->phy, iadev->ram, iadev->seg_ram,
2404 iadev->reass_ram);)
2409 iounmap(iadev->base);
2419 iounmap(iadev->base);
2426 static void ia_update_stats(IADEV *iadev) {
2427 if (!iadev->carrier_detect)
2429 iadev->rx_cell_cnt += readw(iadev->reass_reg+CELL_CTR0)&0xffff;
2430 iadev->rx_cell_cnt += (readw(iadev->reass_reg+CELL_CTR1) & 0xffff) << 16;
2431 iadev->drop_rxpkt += readw(iadev->reass_reg + DRP_PKT_CNTR ) & 0xffff;
2432 iadev->drop_rxcell += readw(iadev->reass_reg + ERR_CNTR) & 0xffff;
2433 iadev->tx_cell_cnt += readw(iadev->seg_reg + CELL_CTR_LO_AUTO)&0xffff;
2434 iadev->tx_cell_cnt += (readw(iadev->seg_reg+CELL_CTR_HIGH_AUTO)&0xffff)<<16;
2479 static void ia_free_tx(IADEV *iadev)
2483 kfree(iadev->desc_tbl);
2484 for (i = 0; i < iadev->num_vc; i++)
2485 kfree(iadev->testTable[i]);
2486 kfree(iadev->testTable);
2487 for (i = 0; i < iadev->num_tx_desc; i++) {
2488 struct cpcs_trailer_desc *desc = iadev->tx_buf + i;
2490 dma_unmap_single(&iadev->pci->dev, desc->dma_addr,
2494 kfree(iadev->tx_buf);
2495 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,
2496 iadev->tx_dle_dma);
2499 static void ia_free_rx(IADEV *iadev)
2501 kfree(iadev->rx_open);
2502 dma_free_coherent(&iadev->pci->dev, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,
2503 iadev->rx_dle_dma);
2508 IADEV *iadev;
2513 iadev = INPH_IA_DEV(dev);
2514 if (request_irq(iadev->irq, &ia_int, IRQF_SHARED, DEV_LABEL, dev)) {
2516 dev->number, iadev->irq);
2522 if ((error = pci_write_config_word(iadev->pci,
2537 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));)
2538 ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2554 writel(ctrl_reg, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2557 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));
2559 readl(iadev->reg+IPHASE5575_BUS_STATUS_REG));)
2561 ia_hw_type(iadev);
2569 ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2570 writel(ctrl_reg | CTRL_FE_RST, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2572 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));)
2580 if (iadev->phy_type & FE_25MBIT_PHY)
2581 ia_mb25_init(iadev);
2582 else if (iadev->phy_type & (FE_DS3_PHY | FE_E3_PHY))
2583 ia_suni_pm7345_init(iadev);
2593 /* Get iadev->carrier_detect status */
2594 ia_frontend_intr(iadev);
2599 ia_free_rx(iadev);
2601 ia_free_tx(iadev);
2603 free_irq(iadev->irq, dev);
2612 IADEV *iadev;
2618 iadev = INPH_IA_DEV(vcc->dev);
2628 iadev->close_pending++;
2629 prepare_to_wait(&iadev->timeout_wait, &wait, TASK_UNINTERRUPTIBLE);
2631 finish_wait(&iadev->timeout_wait, &wait);
2632 spin_lock_irqsave(&iadev->tx_lock, flags);
2633 while((skb = skb_dequeue(&iadev->tx_backlog))) {
2642 skb_queue_tail(&iadev->tx_backlog, skb);
2647 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2648 wait_event_timeout(iadev->close_wait, (ia_vcc->vc_desc_cnt <= 0), closetime);
2649 spin_lock_irqsave(&iadev->tx_lock, flags);
2650 iadev->close_pending--;
2651 iadev->testTable[vcc->vci]->lastTime = 0;
2652 iadev->testTable[vcc->vci]->fract = 0;
2653 iadev->testTable[vcc->vci]->vc_status = VC_UBR;
2656 iadev->sum_mcr -= vcc->qos.txtp.min_pcr;
2660 iadev->sum_mcr -= ia_vcc->NumCbrEntry*iadev->Granularity;
2663 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2668 vc_table = (u16 *)(iadev->reass_ram+REASS_TABLE*iadev->memSize);
2672 vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);
2677 (iadev->reass_ram+ABR_VC_TABLE*iadev->memSize);
2684 iadev->rx_open[vcc->vci] = NULL;
2719 IF_EVENT(printk("iadev: error in open_rx, closing\n");)
2726 IF_EVENT(printk("iadev: error in open_tx, closing\n");)
2756 IADEV *iadev;
2771 iadev = ia_dev[board];
2780 if(put_user((u16)(readl(iadev->seg_reg+i) & 0xffff), tmps)) return -EFAULT;
2788 if(put_user((u16)(readl(iadev->reass_reg+i) & 0xffff), tmps)) return -EFAULT;
2805 ((u_int *)rfL)[i] = readl(iadev->reass_reg + i) & 0xffff;
2808 ((u_int *)ffL)[i] = readl(iadev->seg_reg + i) & 0xffff;
2822 desc_dbg(iadev);
2829 printk("skb = 0x%p\n", skb_peek(&iadev->tx_backlog));
2830 printk("rtn_q: 0x%p\n",ia_deque_rtn_q(&iadev->tx_return_q));
2851 for (i = 1; i <= iadev->num_rx_desc; i++)
2854 iadev->reass_reg+REASS_MASK_REG);
2855 iadev->rxing = 1;
2862 ia_frontend_intr(iadev);
2886 IADEV *iadev;
2895 iadev = INPH_IA_DEV(vcc->dev);
2906 if (skb->len > iadev->tx_buf_sz - 8) {
2927 desc = get_desc (iadev, iavcc);
2933 if ((desc == 0) || (desc > iadev->num_tx_desc))
2952 iadev->desc_tbl[desc-1].iavcc = iavcc;
2953 iadev->desc_tbl[desc-1].txskb = skb;
2956 iadev->ffL.tcq_rd += 2;
2957 if (iadev->ffL.tcq_rd > iadev->ffL.tcq_ed)
2958 iadev->ffL.tcq_rd = iadev->ffL.tcq_st;
2959 writew(iadev->ffL.tcq_rd, iadev->seg_reg+TCQ_RD_PTR);
2964 *(u16*)(iadev->seg_ram+iadev->ffL.prq_wr) = desc;
2966 iadev->ffL.prq_wr += 2;
2967 if (iadev->ffL.prq_wr > iadev->ffL.prq_ed)
2968 iadev->ffL.prq_wr = iadev->ffL.prq_st;
2977 trailer = iadev->tx_buf[desc-1].cpcs;
2992 buf_desc_ptr = iadev->seg_ram+TX_DESC_BASE;
2996 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
3001 clear_lockup (vcc, iadev);
3004 wr_ptr = iadev->tx_dle_q.write;
3006 wr_ptr->sys_pkt_addr = dma_map_single(&iadev->pci->dev, skb->data,
3021 if (++wr_ptr == iadev->tx_dle_q.end)
3022 wr_ptr = iadev->tx_dle_q.start;
3025 wr_ptr->sys_pkt_addr = iadev->tx_buf[desc-1].dma_addr;
3031 wr_ptr->prq_wr_ptr_data = iadev->ffL.prq_wr;
3034 if (++wr_ptr == iadev->tx_dle_q.end)
3035 wr_ptr = iadev->tx_dle_q.start;
3037 iadev->tx_dle_q.write = wr_ptr;
3039 skb_queue_tail(&iadev->tx_dma_q, skb);
3042 iadev->tx_pkt_cnt++;
3044 writel(2, iadev->dma+IPHASE5575_TX_COUNTER);
3067 IADEV *iadev;
3070 iadev = INPH_IA_DEV(vcc->dev);
3071 if ((!skb)||(skb->len>(iadev->tx_buf_sz-sizeof(struct cpcs_trailer))))
3078 spin_lock_irqsave(&iadev->tx_lock, flags);
3081 spin_unlock_irqrestore(&iadev->tx_lock, flags);
3086 if (skb_peek(&iadev->tx_backlog)) {
3087 skb_queue_tail(&iadev->tx_backlog, skb);
3091 skb_queue_tail(&iadev->tx_backlog, skb);
3094 spin_unlock_irqrestore(&iadev->tx_lock, flags);
3103 IADEV *iadev = INPH_IA_DEV(dev);
3105 if (iadev->phy_type == FE_25MBIT_PHY) {
3109 if (iadev->phy_type == FE_DS3_PHY)
3111 else if (iadev->phy_type == FE_E3_PHY)
3113 else if (iadev->phy_type == FE_UTP_OPTION)
3118 if (iadev->pci_map_size == 0x40000)
3123 if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_1M)
3125 else if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_512K)
3142 iadev->num_tx_desc, iadev->tx_buf_sz,
3143 iadev->num_rx_desc, iadev->rx_buf_sz,
3144 iadev->rx_pkt_cnt, iadev->tx_pkt_cnt,
3145 iadev->rx_cell_cnt, iadev->tx_cell_cnt,
3146 iadev->drop_rxcell, iadev->drop_rxpkt);
3166 IADEV *iadev;
3169 iadev = kzalloc(sizeof(*iadev), GFP_KERNEL);
3170 if (!iadev) {
3175 iadev->pci = pdev;
3188 dev->dev_data = iadev;
3190 IF_INIT(printk("dev_id = 0x%p iadev->LineRate = %d \n", dev,
3191 iadev->LineRate);)
3195 ia_dev[iadev_count] = iadev;
3208 iadev->next_board = ia_boards;
3218 kfree(iadev);
3226 IADEV *iadev = INPH_IA_DEV(dev);
3237 free_irq(iadev->irq, dev);
3244 iounmap(iadev->base);
3247 ia_free_rx(iadev);
3248 ia_free_tx(iadev);
3250 kfree(iadev);