Lines Matching refs:he_dev
88 #define hprintk(fmt,args...) printk(KERN_ERR DEV_LABEL "%d: " fmt, he_dev->number , ##args)
91 #define HPRINTK(fmt,args...) printk(KERN_DEBUG DEV_LABEL "%d: " fmt, he_dev->number , ##args)
106 static void he_stop(struct he_dev *dev);
110 static u8 read_prom_byte(struct he_dev *he_dev, int addr);
114 static struct he_dev *he_devs;
182 he_writel_internal(struct he_dev *he_dev, unsigned val, unsigned addr,
185 he_writel(he_dev, val, CON_DAT);
186 (void) he_readl(he_dev, CON_DAT); /* flush posted writes */
187 he_writel(he_dev, flags | CON_CTL_WRITE | CON_CTL_ADDR(addr), CON_CTL);
188 while (he_readl(he_dev, CON_CTL) & CON_CTL_BUSY);
201 he_readl_internal(struct he_dev *he_dev, unsigned addr, unsigned flags)
203 he_writel(he_dev, flags | CON_CTL_READ | CON_CTL_ADDR(addr), CON_CTL);
204 while (he_readl(he_dev, CON_CTL) & CON_CTL_BUSY);
205 return he_readl(he_dev, CON_DAT);
328 __find_vcc(struct he_dev *he_dev, unsigned cid)
336 vpi = cid >> he_dev->vcibits;
337 vci = cid & ((1 << he_dev->vcibits) - 1);
342 if (vcc->dev == he_dev->atm_dev &&
355 struct he_dev *he_dev = NULL;
375 he_dev = kzalloc(sizeof(struct he_dev),
377 if (!he_dev) {
381 he_dev->pci_dev = pci_dev;
382 he_dev->atm_dev = atm_dev;
383 he_dev->atm_dev->dev_data = he_dev;
384 atm_dev->dev_data = he_dev;
385 he_dev->number = atm_dev->number;
386 tasklet_init(&he_dev->tasklet, he_tasklet, (unsigned long) he_dev);
387 spin_lock_init(&he_dev->global_lock);
390 he_stop(he_dev);
394 he_dev->next = NULL;
396 he_dev->next = he_devs;
397 he_devs = he_dev;
403 kfree(he_dev);
411 struct he_dev *he_dev;
414 he_dev = HE_DEV(atm_dev);
418 he_stop(he_dev);
420 kfree(he_dev);
445 static void he_init_rx_lbfp0(struct he_dev *he_dev)
448 unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
449 unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
450 unsigned row_offset = he_dev->r0_startrow * he_dev->bytes_per_row;
453 lbm_offset = he_readl(he_dev, RCMLBM_BA);
455 he_writel(he_dev, lbufd_index, RLBF0_H);
457 for (i = 0, lbuf_count = 0; i < he_dev->r0_numbuffs; ++i) {
461 he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
462 he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);
466 row_offset += he_dev->bytes_per_row;
471 he_writel(he_dev, lbufd_index - 2, RLBF0_T);
472 he_writel(he_dev, he_dev->r0_numbuffs, RLBF0_C);
475 static void he_init_rx_lbfp1(struct he_dev *he_dev)
478 unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
479 unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
480 unsigned row_offset = he_dev->r1_startrow * he_dev->bytes_per_row;
483 lbm_offset = he_readl(he_dev, RCMLBM_BA) + (2 * lbufd_index);
485 he_writel(he_dev, lbufd_index, RLBF1_H);
487 for (i = 0, lbuf_count = 0; i < he_dev->r1_numbuffs; ++i) {
491 he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
492 he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);
496 row_offset += he_dev->bytes_per_row;
501 he_writel(he_dev, lbufd_index - 2, RLBF1_T);
502 he_writel(he_dev, he_dev->r1_numbuffs, RLBF1_C);
505 static void he_init_tx_lbfp(struct he_dev *he_dev)
508 unsigned lbufs_per_row = he_dev->cells_per_row / he_dev->cells_per_lbuf;
509 unsigned lbuf_bufsize = he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD;
510 unsigned row_offset = he_dev->tx_startrow * he_dev->bytes_per_row;
512 lbufd_index = he_dev->r0_numbuffs + he_dev->r1_numbuffs;
513 lbm_offset = he_readl(he_dev, RCMLBM_BA) + (2 * lbufd_index);
515 he_writel(he_dev, lbufd_index, TLBF_H);
517 for (i = 0, lbuf_count = 0; i < he_dev->tx_numbuffs; ++i) {
521 he_writel_rcm(he_dev, lbuf_addr, lbm_offset);
522 he_writel_rcm(he_dev, lbufd_index, lbm_offset + 1);
526 row_offset += he_dev->bytes_per_row;
531 he_writel(he_dev, lbufd_index - 1, TLBF_T);
534 static int he_init_tpdrq(struct he_dev *he_dev)
536 he_dev->tpdrq_base = dma_alloc_coherent(&he_dev->pci_dev->dev,
538 &he_dev->tpdrq_phys,
540 if (he_dev->tpdrq_base == NULL) {
545 he_dev->tpdrq_tail = he_dev->tpdrq_base;
546 he_dev->tpdrq_head = he_dev->tpdrq_base;
548 he_writel(he_dev, he_dev->tpdrq_phys, TPDRQ_B_H);
549 he_writel(he_dev, 0, TPDRQ_T);
550 he_writel(he_dev, CONFIG_TPDRQ_SIZE - 1, TPDRQ_S);
555 static void he_init_cs_block(struct he_dev *he_dev)
563 he_writel_mbox(he_dev, 0x0, CS_STTIM0 + reg);
567 clock = he_is622(he_dev) ? 66667000 : 50000000;
568 rate = he_dev->atm_dev->link_rate;
579 he_writel_mbox(he_dev, period, CS_TGRLD0 + reg);
583 if (he_is622(he_dev)) {
585 he_writel_mbox(he_dev, 0x000800fa, CS_ERTHR0);
586 he_writel_mbox(he_dev, 0x000c33cb, CS_ERTHR1);
587 he_writel_mbox(he_dev, 0x0010101b, CS_ERTHR2);
588 he_writel_mbox(he_dev, 0x00181dac, CS_ERTHR3);
589 he_writel_mbox(he_dev, 0x00280600, CS_ERTHR4);
592 he_writel_mbox(he_dev, 0x023de8b3, CS_ERCTL0);
593 he_writel_mbox(he_dev, 0x1801, CS_ERCTL1);
594 he_writel_mbox(he_dev, 0x68b3, CS_ERCTL2);
595 he_writel_mbox(he_dev, 0x1280, CS_ERSTAT0);
596 he_writel_mbox(he_dev, 0x68b3, CS_ERSTAT1);
597 he_writel_mbox(he_dev, 0x14585, CS_RTFWR);
599 he_writel_mbox(he_dev, 0x4680, CS_RTATR);
602 he_writel_mbox(he_dev, 0x00159ece, CS_TFBSET);
603 he_writel_mbox(he_dev, 0x68b3, CS_WCRMAX);
604 he_writel_mbox(he_dev, 0x5eb3, CS_WCRMIN);
605 he_writel_mbox(he_dev, 0xe8b3, CS_WCRINC);
606 he_writel_mbox(he_dev, 0xdeb3, CS_WCRDEC);
607 he_writel_mbox(he_dev, 0x68b3, CS_WCRCEIL);
610 he_writel_mbox(he_dev, 0x5, CS_OTPPER);
611 he_writel_mbox(he_dev, 0x14, CS_OTWPER);
614 he_writel_mbox(he_dev, 0x000400ea, CS_ERTHR0);
615 he_writel_mbox(he_dev, 0x00063388, CS_ERTHR1);
616 he_writel_mbox(he_dev, 0x00081018, CS_ERTHR2);
617 he_writel_mbox(he_dev, 0x000c1dac, CS_ERTHR3);
618 he_writel_mbox(he_dev, 0x0014051a, CS_ERTHR4);
621 he_writel_mbox(he_dev, 0x0235e4b1, CS_ERCTL0);
622 he_writel_mbox(he_dev, 0x4701, CS_ERCTL1);
623 he_writel_mbox(he_dev, 0x64b1, CS_ERCTL2);
624 he_writel_mbox(he_dev, 0x1280, CS_ERSTAT0);
625 he_writel_mbox(he_dev, 0x64b1, CS_ERSTAT1);
626 he_writel_mbox(he_dev, 0xf424, CS_RTFWR);
628 he_writel_mbox(he_dev, 0x4680, CS_RTATR);
631 he_writel_mbox(he_dev, 0x000563b7, CS_TFBSET);
632 he_writel_mbox(he_dev, 0x64b1, CS_WCRMAX);
633 he_writel_mbox(he_dev, 0x5ab1, CS_WCRMIN);
634 he_writel_mbox(he_dev, 0xe4b1, CS_WCRINC);
635 he_writel_mbox(he_dev, 0xdab1, CS_WCRDEC);
636 he_writel_mbox(he_dev, 0x64b1, CS_WCRCEIL);
639 he_writel_mbox(he_dev, 0x6, CS_OTPPER);
640 he_writel_mbox(he_dev, 0x1e, CS_OTWPER);
643 he_writel_mbox(he_dev, 0x8, CS_OTTLIM);
646 he_writel_mbox(he_dev, 0x0, CS_HGRRT0 + reg);
650 static int he_init_cs_block_rcm(struct he_dev *he_dev)
667 he_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg);
672 he_writel_rcm(he_dev, 0x0, CONFIG_RCMABR + reg);
682 rate = he_dev->atm_dev->link_rate;
737 buf = rate_cps * he_dev->tx_numbuffs /
738 (he_dev->atm_dev->link_rate * 2);
741 mult = he_dev->atm_dev->link_rate / ATM_OC3_PCR;
760 he_writel_rcm(he_dev, reg,
770 static int he_init_group(struct he_dev *he_dev, int group)
776 he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));
777 he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));
778 he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));
779 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
783 he_dev->rbpl_table = kmalloc_array(BITS_TO_LONGS(RBPL_TABLE_SIZE),
784 sizeof(*he_dev->rbpl_table),
786 if (!he_dev->rbpl_table) {
790 bitmap_zero(he_dev->rbpl_table, RBPL_TABLE_SIZE);
793 he_dev->rbpl_virt = kmalloc_array(RBPL_TABLE_SIZE,
794 sizeof(*he_dev->rbpl_virt),
796 if (!he_dev->rbpl_virt) {
802 he_dev->rbpl_pool = dma_pool_create("rbpl", &he_dev->pci_dev->dev,
804 if (he_dev->rbpl_pool == NULL) {
809 he_dev->rbpl_base = dma_alloc_coherent(&he_dev->pci_dev->dev,
811 &he_dev->rbpl_phys, GFP_KERNEL);
812 if (he_dev->rbpl_base == NULL) {
817 INIT_LIST_HEAD(&he_dev->rbpl_outstanding);
821 heb = dma_pool_alloc(he_dev->rbpl_pool, GFP_KERNEL, &mapping);
825 list_add(&heb->entry, &he_dev->rbpl_outstanding);
827 set_bit(i, he_dev->rbpl_table);
828 he_dev->rbpl_virt[i] = heb;
829 he_dev->rbpl_hint = i + 1;
830 he_dev->rbpl_base[i].idx = i << RBP_IDX_OFFSET;
831 he_dev->rbpl_base[i].phys = mapping + offsetof(struct he_buff, data);
833 he_dev->rbpl_tail = &he_dev->rbpl_base[CONFIG_RBPL_SIZE - 1];
835 he_writel(he_dev, he_dev->rbpl_phys, G0_RBPL_S + (group * 32));
836 he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail),
838 he_writel(he_dev, (CONFIG_RBPL_BUFSIZE - sizeof(struct he_buff))/4,
840 he_writel(he_dev,
848 he_dev->rbrq_base = dma_alloc_coherent(&he_dev->pci_dev->dev,
850 &he_dev->rbrq_phys, GFP_KERNEL);
851 if (he_dev->rbrq_base == NULL) {
856 he_dev->rbrq_head = he_dev->rbrq_base;
857 he_writel(he_dev, he_dev->rbrq_phys, G0_RBRQ_ST + (group * 16));
858 he_writel(he_dev, 0, G0_RBRQ_H + (group * 16));
859 he_writel(he_dev,
864 he_writel(he_dev, RBRQ_TIME(768) | RBRQ_COUNT(7),
867 he_writel(he_dev, RBRQ_TIME(0) | RBRQ_COUNT(1),
872 he_dev->tbrq_base = dma_alloc_coherent(&he_dev->pci_dev->dev,
874 &he_dev->tbrq_phys, GFP_KERNEL);
875 if (he_dev->tbrq_base == NULL) {
880 he_dev->tbrq_head = he_dev->tbrq_base;
882 he_writel(he_dev, he_dev->tbrq_phys, G0_TBRQ_B_T + (group * 16));
883 he_writel(he_dev, 0, G0_TBRQ_H + (group * 16));
884 he_writel(he_dev, CONFIG_TBRQ_SIZE - 1, G0_TBRQ_S + (group * 16));
885 he_writel(he_dev, CONFIG_TBRQ_THRESH, G0_TBRQ_THRESH + (group * 16));
890 dma_free_coherent(&he_dev->pci_dev->dev, CONFIG_RBRQ_SIZE *
891 sizeof(struct he_rbrq), he_dev->rbrq_base,
892 he_dev->rbrq_phys);
894 list_for_each_entry_safe(heb, next, &he_dev->rbpl_outstanding, entry)
895 dma_pool_free(he_dev->rbpl_pool, heb, heb->mapping);
897 dma_free_coherent(&he_dev->pci_dev->dev, CONFIG_RBPL_SIZE *
898 sizeof(struct he_rbp), he_dev->rbpl_base,
899 he_dev->rbpl_phys);
901 dma_pool_destroy(he_dev->rbpl_pool);
903 kfree(he_dev->rbpl_virt);
905 kfree(he_dev->rbpl_table);
910 static int he_init_irq(struct he_dev *he_dev)
917 he_dev->irq_base = dma_alloc_coherent(&he_dev->pci_dev->dev,
919 &he_dev->irq_phys, GFP_KERNEL);
920 if (he_dev->irq_base == NULL) {
924 he_dev->irq_tailoffset = (unsigned *)
925 &he_dev->irq_base[CONFIG_IRQ_SIZE];
926 *he_dev->irq_tailoffset = 0;
927 he_dev->irq_head = he_dev->irq_base;
928 he_dev->irq_tail = he_dev->irq_base;
931 he_dev->irq_base[i].isw = ITYPE_INVALID;
933 he_writel(he_dev, he_dev->irq_phys, IRQ0_BASE);
934 he_writel(he_dev,
937 he_writel(he_dev, IRQ_INT_A | IRQ_TYPE_LINE, IRQ0_CNTL);
938 he_writel(he_dev, 0x0, IRQ0_DATA);
940 he_writel(he_dev, 0x0, IRQ1_BASE);
941 he_writel(he_dev, 0x0, IRQ1_HEAD);
942 he_writel(he_dev, 0x0, IRQ1_CNTL);
943 he_writel(he_dev, 0x0, IRQ1_DATA);
945 he_writel(he_dev, 0x0, IRQ2_BASE);
946 he_writel(he_dev, 0x0, IRQ2_HEAD);
947 he_writel(he_dev, 0x0, IRQ2_CNTL);
948 he_writel(he_dev, 0x0, IRQ2_DATA);
950 he_writel(he_dev, 0x0, IRQ3_BASE);
951 he_writel(he_dev, 0x0, IRQ3_HEAD);
952 he_writel(he_dev, 0x0, IRQ3_CNTL);
953 he_writel(he_dev, 0x0, IRQ3_DATA);
957 he_writel(he_dev, 0x0, GRP_10_MAP);
958 he_writel(he_dev, 0x0, GRP_32_MAP);
959 he_writel(he_dev, 0x0, GRP_54_MAP);
960 he_writel(he_dev, 0x0, GRP_76_MAP);
962 if (request_irq(he_dev->pci_dev->irq,
963 he_irq_handler, IRQF_SHARED, DEV_LABEL, he_dev)) {
964 hprintk("irq %d already in use\n", he_dev->pci_dev->irq);
968 he_dev->irq = he_dev->pci_dev->irq;
975 struct he_dev *he_dev;
987 he_dev = HE_DEV(dev);
988 pci_dev = he_dev->pci_dev;
1051 if (!(he_dev->membase = ioremap(membase, HE_REGMAP_SIZE))) {
1057 he_writel(he_dev, 0x0, RESET_CNTL);
1058 he_writel(he_dev, 0xff, RESET_CNTL);
1061 status = he_readl(he_dev, RESET_CNTL);
1068 host_cntl = he_readl(he_dev, HOST_CNTL);
1086 he_dev->prod_id[i] = read_prom_byte(he_dev, PROD_ID + i);
1088 he_dev->media = read_prom_byte(he_dev, MEDIA);
1091 dev->esi[i] = read_prom_byte(he_dev, MAC_ADDR + i);
1093 hprintk("%s%s, %pM\n", he_dev->prod_id,
1094 he_dev->media & 0x40 ? "SM" : "MM", dev->esi);
1095 he_dev->atm_dev->link_rate = he_is622(he_dev) ?
1099 lb_swap = he_readl(he_dev, LB_SWAP);
1100 if (he_is622(he_dev))
1110 he_writel(he_dev, lb_swap, LB_SWAP);
1113 he_writel(he_dev, he_is622(he_dev) ? LB_64_ENB : 0x0, SDRAM_CTL);
1117 he_writel(he_dev, lb_swap, LB_SWAP);
1120 if ((err = he_init_irq(he_dev)) != 0)
1126 he_writel(he_dev, host_cntl, HOST_CNTL);
1166 he_dev->vcibits = CONFIG_DEFAULT_VCIBITS;
1167 he_dev->vpibits = CONFIG_DEFAULT_VPIBITS;
1175 he_dev->vpibits = nvpibits;
1176 he_dev->vcibits = HE_MAXCIDBITS - nvpibits;
1180 he_dev->vcibits = nvcibits;
1181 he_dev->vpibits = HE_MAXCIDBITS - nvcibits;
1185 if (he_is622(he_dev)) {
1186 he_dev->cells_per_row = 40;
1187 he_dev->bytes_per_row = 2048;
1188 he_dev->r0_numrows = 256;
1189 he_dev->tx_numrows = 512;
1190 he_dev->r1_numrows = 256;
1191 he_dev->r0_startrow = 0;
1192 he_dev->tx_startrow = 256;
1193 he_dev->r1_startrow = 768;
1195 he_dev->cells_per_row = 20;
1196 he_dev->bytes_per_row = 1024;
1197 he_dev->r0_numrows = 512;
1198 he_dev->tx_numrows = 1018;
1199 he_dev->r1_numrows = 512;
1200 he_dev->r0_startrow = 6;
1201 he_dev->tx_startrow = 518;
1202 he_dev->r1_startrow = 1536;
1205 he_dev->cells_per_lbuf = 4;
1206 he_dev->buffer_limit = 4;
1207 he_dev->r0_numbuffs = he_dev->r0_numrows *
1208 he_dev->cells_per_row / he_dev->cells_per_lbuf;
1209 if (he_dev->r0_numbuffs > 2560)
1210 he_dev->r0_numbuffs = 2560;
1212 he_dev->r1_numbuffs = he_dev->r1_numrows *
1213 he_dev->cells_per_row / he_dev->cells_per_lbuf;
1214 if (he_dev->r1_numbuffs > 2560)
1215 he_dev->r1_numbuffs = 2560;
1217 he_dev->tx_numbuffs = he_dev->tx_numrows *
1218 he_dev->cells_per_row / he_dev->cells_per_lbuf;
1219 if (he_dev->tx_numbuffs > 5120)
1220 he_dev->tx_numbuffs = 5120;
1224 he_writel(he_dev,
1227 (he_is622(he_dev) ? BUS_MULTI(0x28) : BUS_MULTI(0x46)) |
1228 (he_is622(he_dev) ? NET_PREF(0x50) : NET_PREF(0x8c)),
1231 he_writel(he_dev, BANK_ON |
1232 (he_is622(he_dev) ? (REF_RATE(0x384) | WIDE_DATA) : REF_RATE(0x150)),
1235 he_writel(he_dev,
1236 (he_is622(he_dev) ? RM_BANK_WAIT(1) : RM_BANK_WAIT(0)) |
1238 he_writel(he_dev,
1239 (he_is622(he_dev) ? TM_BANK_WAIT(2) : TM_BANK_WAIT(1)) |
1242 he_writel(he_dev, he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD, LB_CONFIG);
1244 he_writel(he_dev,
1245 (he_is622(he_dev) ? UT_RD_DELAY(8) : UT_RD_DELAY(0)) |
1246 (he_is622(he_dev) ? RC_UT_MODE(0) : RC_UT_MODE(1)) |
1247 RX_VALVP(he_dev->vpibits) |
1248 RX_VALVC(he_dev->vcibits), RC_CONFIG);
1250 he_writel(he_dev, DRF_THRESH(0x20) |
1251 (he_is622(he_dev) ? TX_UT_MODE(0) : TX_UT_MODE(1)) |
1252 TX_VCI_MASK(he_dev->vcibits) |
1253 LBFREE_CNT(he_dev->tx_numbuffs), TX_CONFIG);
1255 he_writel(he_dev, 0x0, TXAAL5_PROTO);
1257 he_writel(he_dev, PHY_INT_ENB |
1258 (he_is622(he_dev) ? PTMR_PRE(67 - 1) : PTMR_PRE(50 - 1)),
1264 he_writel_tcm(he_dev, 0, i);
1267 he_writel_rcm(he_dev, 0, i);
1300 he_writel(he_dev, CONFIG_TSRB, TSRB_BA);
1301 he_writel(he_dev, CONFIG_TSRC, TSRC_BA);
1302 he_writel(he_dev, CONFIG_TSRD, TSRD_BA);
1303 he_writel(he_dev, CONFIG_TMABR, TMABR_BA);
1304 he_writel(he_dev, CONFIG_TPDBA, TPD_BA);
1334 he_writel(he_dev, 0x08000, RCMLBM_BA);
1335 he_writel(he_dev, 0x0e000, RCMRSRB_BA);
1336 he_writel(he_dev, 0x0d800, RCMABR_BA);
1340 he_init_rx_lbfp0(he_dev);
1341 he_init_rx_lbfp1(he_dev);
1343 he_writel(he_dev, 0x0, RLBC_H);
1344 he_writel(he_dev, 0x0, RLBC_T);
1345 he_writel(he_dev, 0x0, RLBC_H2);
1347 he_writel(he_dev, 512, RXTHRSH); /* 10% of r0+r1 buffers */
1348 he_writel(he_dev, 256, LITHRSH); /* 5% of r0+r1 buffers */
1350 he_init_tx_lbfp(he_dev);
1352 he_writel(he_dev, he_is622(he_dev) ? 0x104780 : 0x800, UBUFF_BA);
1356 if (he_is622(he_dev)) {
1357 he_writel(he_dev, 0x000f, G0_INMQ_S);
1358 he_writel(he_dev, 0x200f, G0_INMQ_L);
1360 he_writel(he_dev, 0x001f, G1_INMQ_S);
1361 he_writel(he_dev, 0x201f, G1_INMQ_L);
1363 he_writel(he_dev, 0x002f, G2_INMQ_S);
1364 he_writel(he_dev, 0x202f, G2_INMQ_L);
1366 he_writel(he_dev, 0x003f, G3_INMQ_S);
1367 he_writel(he_dev, 0x203f, G3_INMQ_L);
1369 he_writel(he_dev, 0x004f, G4_INMQ_S);
1370 he_writel(he_dev, 0x204f, G4_INMQ_L);
1372 he_writel(he_dev, 0x005f, G5_INMQ_S);
1373 he_writel(he_dev, 0x205f, G5_INMQ_L);
1375 he_writel(he_dev, 0x006f, G6_INMQ_S);
1376 he_writel(he_dev, 0x206f, G6_INMQ_L);
1378 he_writel(he_dev, 0x007f, G7_INMQ_S);
1379 he_writel(he_dev, 0x207f, G7_INMQ_L);
1381 he_writel(he_dev, 0x0000, G0_INMQ_S);
1382 he_writel(he_dev, 0x0008, G0_INMQ_L);
1384 he_writel(he_dev, 0x0001, G1_INMQ_S);
1385 he_writel(he_dev, 0x0009, G1_INMQ_L);
1387 he_writel(he_dev, 0x0002, G2_INMQ_S);
1388 he_writel(he_dev, 0x000a, G2_INMQ_L);
1390 he_writel(he_dev, 0x0003, G3_INMQ_S);
1391 he_writel(he_dev, 0x000b, G3_INMQ_L);
1393 he_writel(he_dev, 0x0004, G4_INMQ_S);
1394 he_writel(he_dev, 0x000c, G4_INMQ_L);
1396 he_writel(he_dev, 0x0005, G5_INMQ_S);
1397 he_writel(he_dev, 0x000d, G5_INMQ_L);
1399 he_writel(he_dev, 0x0006, G6_INMQ_S);
1400 he_writel(he_dev, 0x000e, G6_INMQ_L);
1402 he_writel(he_dev, 0x0007, G7_INMQ_S);
1403 he_writel(he_dev, 0x000f, G7_INMQ_L);
1408 he_writel(he_dev, 0x0, MCC);
1409 he_writel(he_dev, 0x0, OEC);
1410 he_writel(he_dev, 0x0, DCC);
1411 he_writel(he_dev, 0x0, CEC);
1415 he_init_cs_block(he_dev);
1419 if (he_init_cs_block_rcm(he_dev) < 0)
1424 he_init_tpdrq(he_dev);
1426 he_dev->tpd_pool = dma_pool_create("tpd", &he_dev->pci_dev->dev,
1428 if (he_dev->tpd_pool == NULL) {
1433 INIT_LIST_HEAD(&he_dev->outstanding_tpds);
1435 if (he_init_group(he_dev, 0) != 0)
1439 he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));
1440 he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));
1441 he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));
1442 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
1445 he_writel(he_dev, 0x0, G0_RBPL_S + (group * 32));
1446 he_writel(he_dev, 0x0, G0_RBPL_T + (group * 32));
1447 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
1449 he_writel(he_dev, 0x0, G0_RBPL_BS + (group * 32));
1451 he_writel(he_dev, 0x0, G0_RBRQ_ST + (group * 16));
1452 he_writel(he_dev, 0x0, G0_RBRQ_H + (group * 16));
1453 he_writel(he_dev, RBRQ_THRESH(0x1) | RBRQ_SIZE(0x0),
1455 he_writel(he_dev, 0x0, G0_RBRQ_I + (group * 16));
1457 he_writel(he_dev, 0x0, G0_TBRQ_B_T + (group * 16));
1458 he_writel(he_dev, 0x0, G0_TBRQ_H + (group * 16));
1459 he_writel(he_dev, TBRQ_THRESH(0x1),
1461 he_writel(he_dev, 0x0, G0_TBRQ_S + (group * 16));
1466 he_dev->hsp = dma_alloc_coherent(&he_dev->pci_dev->dev,
1468 &he_dev->hsp_phys, GFP_KERNEL);
1469 if (he_dev->hsp == NULL) {
1473 he_writel(he_dev, he_dev->hsp_phys, HSP_BA);
1478 if (he_isMM(he_dev))
1479 suni_init(he_dev->atm_dev);
1480 if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->start)
1481 he_dev->atm_dev->phy->start(he_dev->atm_dev);
1488 val = he_phy_get(he_dev->atm_dev, SUNI_TPOP_APM);
1490 he_phy_put(he_dev->atm_dev, val, SUNI_TPOP_APM);
1491 he_phy_put(he_dev->atm_dev, SUNI_TACP_IUCHP_CLP, SUNI_TACP_IUCHP);
1496 reg = he_readl_mbox(he_dev, CS_ERCTL0);
1498 he_writel_mbox(he_dev, reg, CS_ERCTL0);
1500 reg = he_readl(he_dev, RC_CONFIG);
1502 he_writel(he_dev, reg, RC_CONFIG);
1505 he_dev->cs_stper[i].inuse = 0;
1506 he_dev->cs_stper[i].pcr = -1;
1508 he_dev->total_bw = 0;
1513 he_dev->atm_dev->ci_range.vpi_bits = he_dev->vpibits;
1514 he_dev->atm_dev->ci_range.vci_bits = he_dev->vcibits;
1516 he_dev->irq_peak = 0;
1517 he_dev->rbrq_peak = 0;
1518 he_dev->rbpl_peak = 0;
1519 he_dev->tbrq_peak = 0;
1527 he_stop(struct he_dev *he_dev)
1534 pci_dev = he_dev->pci_dev;
1538 if (he_dev->membase) {
1543 tasklet_disable(&he_dev->tasklet);
1547 reg = he_readl_mbox(he_dev, CS_ERCTL0);
1549 he_writel_mbox(he_dev, reg, CS_ERCTL0);
1551 reg = he_readl(he_dev, RC_CONFIG);
1553 he_writel(he_dev, reg, RC_CONFIG);
1557 if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->stop)
1558 he_dev->atm_dev->phy->stop(he_dev->atm_dev);
1561 if (he_dev->irq)
1562 free_irq(he_dev->irq, he_dev);
1564 if (he_dev->irq_base)
1565 dma_free_coherent(&he_dev->pci_dev->dev, (CONFIG_IRQ_SIZE + 1)
1566 * sizeof(struct he_irq), he_dev->irq_base, he_dev->irq_phys);
1568 if (he_dev->hsp)
1569 dma_free_coherent(&he_dev->pci_dev->dev, sizeof(struct he_hsp),
1570 he_dev->hsp, he_dev->hsp_phys);
1572 if (he_dev->rbpl_base) {
1573 list_for_each_entry_safe(heb, next, &he_dev->rbpl_outstanding, entry)
1574 dma_pool_free(he_dev->rbpl_pool, heb, heb->mapping);
1576 dma_free_coherent(&he_dev->pci_dev->dev, CONFIG_RBPL_SIZE
1577 * sizeof(struct he_rbp), he_dev->rbpl_base, he_dev->rbpl_phys);
1580 kfree(he_dev->rbpl_virt);
1581 kfree(he_dev->rbpl_table);
1582 dma_pool_destroy(he_dev->rbpl_pool);
1584 if (he_dev->rbrq_base)
1585 dma_free_coherent(&he_dev->pci_dev->dev, CONFIG_RBRQ_SIZE * sizeof(struct he_rbrq),
1586 he_dev->rbrq_base, he_dev->rbrq_phys);
1588 if (he_dev->tbrq_base)
1589 dma_free_coherent(&he_dev->pci_dev->dev, CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq),
1590 he_dev->tbrq_base, he_dev->tbrq_phys);
1592 if (he_dev->tpdrq_base)
1593 dma_free_coherent(&he_dev->pci_dev->dev, CONFIG_TBRQ_SIZE * sizeof(struct he_tbrq),
1594 he_dev->tpdrq_base, he_dev->tpdrq_phys);
1596 dma_pool_destroy(he_dev->tpd_pool);
1598 if (he_dev->pci_dev) {
1599 pci_read_config_word(he_dev->pci_dev, PCI_COMMAND, &command);
1601 pci_write_config_word(he_dev->pci_dev, PCI_COMMAND, command);
1604 if (he_dev->membase)
1605 iounmap(he_dev->membase);
1609 __alloc_tpd(struct he_dev *he_dev)
1614 tpd = dma_pool_alloc(he_dev->tpd_pool, GFP_ATOMIC, &mapping);
1642 he_service_rbrq(struct he_dev *he_dev, int group)
1645 ((unsigned long)he_dev->rbrq_base |
1646 he_dev->hsp->group[group].rbrq_tail);
1657 while (he_dev->rbrq_head != rbrq_tail) {
1661 he_dev->rbrq_head, group,
1662 RBRQ_ADDR(he_dev->rbrq_head),
1663 RBRQ_BUFLEN(he_dev->rbrq_head),
1664 RBRQ_CID(he_dev->rbrq_head),
1665 RBRQ_CRC_ERR(he_dev->rbrq_head) ? " CRC_ERR" : "",
1666 RBRQ_LEN_ERR(he_dev->rbrq_head) ? " LEN_ERR" : "",
1667 RBRQ_END_PDU(he_dev->rbrq_head) ? " END_PDU" : "",
1668 RBRQ_AAL5_PROT(he_dev->rbrq_head) ? " AAL5_PROT" : "",
1669 RBRQ_CON_CLOSED(he_dev->rbrq_head) ? " CON_CLOSED" : "",
1670 RBRQ_HBUF_ERR(he_dev->rbrq_head) ? " HBUF_ERR" : "");
1672 i = RBRQ_ADDR(he_dev->rbrq_head) >> RBP_IDX_OFFSET;
1673 heb = he_dev->rbpl_virt[i];
1675 cid = RBRQ_CID(he_dev->rbrq_head);
1677 vcc = __find_vcc(he_dev, cid);
1682 if (!RBRQ_HBUF_ERR(he_dev->rbrq_head)) {
1683 clear_bit(i, he_dev->rbpl_table);
1685 dma_pool_free(he_dev->rbpl_pool, heb, heb->mapping);
1691 if (RBRQ_HBUF_ERR(he_dev->rbrq_head)) {
1697 heb->len = RBRQ_BUFLEN(he_dev->rbrq_head) * 4;
1698 clear_bit(i, he_dev->rbpl_table);
1702 if (RBRQ_CON_CLOSED(he_dev->rbrq_head)) {
1709 if (!RBRQ_END_PDU(he_dev->rbrq_head))
1712 if (RBRQ_LEN_ERR(he_dev->rbrq_head)
1713 || RBRQ_CRC_ERR(he_dev->rbrq_head)) {
1715 RBRQ_CRC_ERR(he_dev->rbrq_head)
1717 RBRQ_LEN_ERR(he_dev->rbrq_head)
1768 spin_unlock(&he_dev->global_lock);
1770 spin_lock(&he_dev->global_lock);
1778 dma_pool_free(he_dev->rbpl_pool, heb, heb->mapping);
1783 he_dev->rbrq_head = (struct he_rbrq *)
1784 ((unsigned long) he_dev->rbrq_base |
1785 RBRQ_MASK(he_dev->rbrq_head + 1));
1791 if (updated > he_dev->rbrq_peak)
1792 he_dev->rbrq_peak = updated;
1794 he_writel(he_dev, RBRQ_MASK(he_dev->rbrq_head),
1802 he_service_tbrq(struct he_dev *he_dev, int group)
1805 ((unsigned long)he_dev->tbrq_base |
1806 he_dev->hsp->group[group].tbrq_tail);
1813 while (he_dev->tbrq_head != tbrq_tail) {
1818 TBRQ_TPD(he_dev->tbrq_head),
1819 TBRQ_EOS(he_dev->tbrq_head) ? " EOS" : "",
1820 TBRQ_MULTIPLE(he_dev->tbrq_head) ? " MULTIPLE" : "");
1822 list_for_each_entry(__tpd, &he_dev->outstanding_tpds, entry) {
1823 if (TPD_ADDR(__tpd->status) == TBRQ_TPD(he_dev->tbrq_head)) {
1832 TBRQ_TPD(he_dev->tbrq_head));
1836 if (TBRQ_EOS(he_dev->tbrq_head)) {
1838 he_mkcid(he_dev, tpd->vcc->vpi, tpd->vcc->vci));
1847 dma_unmap_single(&he_dev->pci_dev->dev,
1856 if (tpd->skb) { /* && !TBRQ_MULTIPLE(he_dev->tbrq_head) */
1865 dma_pool_free(he_dev->tpd_pool, tpd, TPD_ADDR(tpd->status));
1866 he_dev->tbrq_head = (struct he_tbrq *)
1867 ((unsigned long) he_dev->tbrq_base |
1868 TBRQ_MASK(he_dev->tbrq_head + 1));
1872 if (updated > he_dev->tbrq_peak)
1873 he_dev->tbrq_peak = updated;
1875 he_writel(he_dev, TBRQ_MASK(he_dev->tbrq_head),
1881 he_service_rbpl(struct he_dev *he_dev, int group)
1890 rbpl_head = (struct he_rbp *) ((unsigned long)he_dev->rbpl_base |
1891 RBPL_MASK(he_readl(he_dev, G0_RBPL_S)));
1894 new_tail = (struct he_rbp *) ((unsigned long)he_dev->rbpl_base |
1895 RBPL_MASK(he_dev->rbpl_tail+1));
1901 i = find_next_zero_bit(he_dev->rbpl_table, RBPL_TABLE_SIZE, he_dev->rbpl_hint);
1903 i = find_first_zero_bit(he_dev->rbpl_table, RBPL_TABLE_SIZE);
1907 he_dev->rbpl_hint = i + 1;
1909 heb = dma_pool_alloc(he_dev->rbpl_pool, GFP_ATOMIC, &mapping);
1913 list_add(&heb->entry, &he_dev->rbpl_outstanding);
1914 he_dev->rbpl_virt[i] = heb;
1915 set_bit(i, he_dev->rbpl_table);
1919 he_dev->rbpl_tail = new_tail;
1924 he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail), G0_RBPL_T);
1931 struct he_dev *he_dev = (struct he_dev *) data;
1936 spin_lock_irqsave(&he_dev->global_lock, flags);
1938 while (he_dev->irq_head != he_dev->irq_tail) {
1941 type = ITYPE_TYPE(he_dev->irq_head->isw);
1942 group = ITYPE_GROUP(he_dev->irq_head->isw);
1949 if (he_service_rbrq(he_dev, group))
1950 he_service_rbpl(he_dev, group);
1956 he_service_tbrq(he_dev, group);
1959 he_service_rbpl(he_dev, group);
1967 spin_unlock_irqrestore(&he_dev->global_lock, flags);
1968 if (he_dev->atm_dev->phy && he_dev->atm_dev->phy->interrupt)
1969 he_dev->atm_dev->phy->interrupt(he_dev->atm_dev);
1970 spin_lock_irqsave(&he_dev->global_lock, flags);
1979 hprintk("abort 0x%x\n", he_readl(he_dev, ABORT_ADDR));
1986 HPRINTK("isw not updated 0x%x\n", he_dev->irq_head->isw);
1988 he_service_rbrq(he_dev, 0);
1989 he_service_rbpl(he_dev, 0);
1990 he_service_tbrq(he_dev, 0);
1993 hprintk("bad isw 0x%x?\n", he_dev->irq_head->isw);
1996 he_dev->irq_head->isw = ITYPE_INVALID;
1998 he_dev->irq_head = (struct he_irq *) NEXT_ENTRY(he_dev->irq_base, he_dev->irq_head, IRQ_MASK);
2002 if (updated > he_dev->irq_peak)
2003 he_dev->irq_peak = updated;
2005 he_writel(he_dev,
2008 IRQ_TAIL(he_dev->irq_tail), IRQ0_HEAD);
2009 (void) he_readl(he_dev, INT_FIFO); /* 8.1.2 controller errata; flush posted writes */
2011 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2018 struct he_dev *he_dev = (struct he_dev * )dev_id;
2021 if (he_dev == NULL)
2024 spin_lock_irqsave(&he_dev->global_lock, flags);
2026 he_dev->irq_tail = (struct he_irq *) (((unsigned long)he_dev->irq_base) |
2027 (*he_dev->irq_tailoffset << 2));
2029 if (he_dev->irq_tail == he_dev->irq_head) {
2031 he_dev->irq_tail = (struct he_irq *) ((unsigned long)he_dev->irq_base |
2032 ((he_readl(he_dev, IRQ0_BASE) & IRQ_MASK) << 2));
2033 (void) he_readl(he_dev, INT_FIFO); /* 8.1.2 controller errata */
2037 if (he_dev->irq_head == he_dev->irq_tail /* && !IRQ_PENDING */)
2041 if (he_dev->irq_head != he_dev->irq_tail) {
2043 tasklet_schedule(&he_dev->tasklet);
2044 he_writel(he_dev, INT_CLEAR_A, INT_FIFO); /* clear interrupt */
2045 (void) he_readl(he_dev, INT_FIFO); /* flush posted writes */
2047 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2053 __enqueue_tpd(struct he_dev *he_dev, struct he_tpd *tpd, unsigned cid)
2058 tpd, cid, he_dev->tpdrq_tail);
2060 /* new_tail = he_dev->tpdrq_tail; */
2061 new_tail = (struct he_tpdrq *) ((unsigned long) he_dev->tpdrq_base |
2062 TPDRQ_MASK(he_dev->tpdrq_tail+1));
2071 if (new_tail == he_dev->tpdrq_head) {
2072 he_dev->tpdrq_head = (struct he_tpdrq *)
2073 (((unsigned long)he_dev->tpdrq_base) |
2074 TPDRQ_MASK(he_readl(he_dev, TPDRQ_B_H)));
2076 if (new_tail == he_dev->tpdrq_head) {
2088 dma_unmap_single(&he_dev->pci_dev->dev,
2100 dma_pool_free(he_dev->tpd_pool, tpd, TPD_ADDR(tpd->status));
2106 list_add_tail(&tpd->entry, &he_dev->outstanding_tpds);
2107 he_dev->tpdrq_tail->tpd = TPD_ADDR(tpd->status);
2108 he_dev->tpdrq_tail->cid = cid;
2111 he_dev->tpdrq_tail = new_tail;
2113 he_writel(he_dev, TPDRQ_MASK(he_dev->tpdrq_tail), TPDRQ_T);
2114 (void) he_readl(he_dev, TPDRQ_T); /* flush posted writes */
2121 struct he_dev *he_dev = HE_DEV(vcc->dev);
2135 cid = he_mkcid(he_dev, vpi, vci);
2157 pcr_goal = he_dev->atm_dev->link_rate;
2177 spin_lock_irqsave(&he_dev->global_lock, flags);
2178 tsr0 = he_readl_tsr0(he_dev, cid);
2179 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2199 if ((he_dev->total_bw + pcr_goal)
2200 > (he_dev->atm_dev->link_rate * 9 / 10))
2206 spin_lock_irqsave(&he_dev->global_lock, flags); /* also protects he_dev->cs_stper[] */
2210 if (he_dev->cs_stper[reg].inuse == 0 ||
2211 he_dev->cs_stper[reg].pcr == pcr_goal)
2216 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2220 he_dev->total_bw += pcr_goal;
2223 ++he_dev->cs_stper[reg].inuse;
2224 he_dev->cs_stper[reg].pcr = pcr_goal;
2226 clock = he_is622(he_dev) ? 66667000 : 50000000;
2232 he_writel_mbox(he_dev, rate_to_atmf(period/2),
2234 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2245 spin_lock_irqsave(&he_dev->global_lock, flags);
2247 he_writel_tsr0(he_dev, tsr0, cid);
2248 he_writel_tsr4(he_dev, tsr4 | 1, cid);
2249 he_writel_tsr1(he_dev, TSR1_MCR(rate_to_atmf(0)) |
2251 he_writel_tsr2(he_dev, TSR2_ACR(rate_to_atmf(pcr_goal)), cid);
2252 he_writel_tsr9(he_dev, TSR9_OPEN_CONN, cid);
2254 he_writel_tsr3(he_dev, 0x0, cid);
2255 he_writel_tsr5(he_dev, 0x0, cid);
2256 he_writel_tsr6(he_dev, 0x0, cid);
2257 he_writel_tsr7(he_dev, 0x0, cid);
2258 he_writel_tsr8(he_dev, 0x0, cid);
2259 he_writel_tsr10(he_dev, 0x0, cid);
2260 he_writel_tsr11(he_dev, 0x0, cid);
2261 he_writel_tsr12(he_dev, 0x0, cid);
2262 he_writel_tsr13(he_dev, 0x0, cid);
2263 he_writel_tsr14(he_dev, 0x0, cid);
2264 (void) he_readl_tsr0(he_dev, cid); /* flush posted writes */
2265 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2286 spin_lock_irqsave(&he_dev->global_lock, flags);
2288 rsr0 = he_readl_rsr0(he_dev, cid);
2290 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2307 he_writel_rsr4(he_dev, rsr4, cid);
2308 he_writel_rsr1(he_dev, rsr1, cid);
2311 he_writel_rsr0(he_dev,
2313 (void) he_readl_rsr0(he_dev, cid); /* flush posted writes */
2315 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2335 struct he_dev *he_dev = HE_DEV(vcc->dev);
2345 cid = he_mkcid(he_dev, vcc->vpi, vcc->vci);
2356 spin_lock_irqsave(&he_dev->global_lock, flags);
2357 while (he_readl(he_dev, RCC_STAT) & RCC_BUSY) {
2365 he_writel_rsr0(he_dev, RSR0_CLOSE_CONN, cid);
2366 (void) he_readl_rsr0(he_dev, cid); /* flush posted writes */
2367 he_writel_mbox(he_dev, cid, RXCON_CLOSE);
2368 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2411 spin_lock_irqsave(&he_dev->global_lock, flags);
2412 he_writel_tsr4_upper(he_dev, TSR4_FLUSH_CONN, cid);
2417 he_writel_tsr1(he_dev,
2422 he_writel_tsr14_upper(he_dev, TSR14_DELETE, cid);
2425 (void) he_readl_tsr4(he_dev, cid); /* flush posted writes */
2427 tpd = __alloc_tpd(he_dev);
2439 __enqueue_tpd(he_dev, tpd, cid);
2440 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2447 spin_lock_irqsave(&he_dev->global_lock, flags);
2454 while (!((tsr4 = he_readl_tsr4(he_dev, cid)) & TSR4_SESSION_ENDED)) {
2459 while (TSR0_CONN_STATE(tsr0 = he_readl_tsr0(he_dev, cid)) != 0) {
2471 if (he_dev->cs_stper[reg].inuse == 0)
2474 --he_dev->cs_stper[reg].inuse;
2476 he_dev->total_bw -= he_dev->cs_stper[reg].pcr;
2478 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2492 struct he_dev *he_dev = HE_DEV(vcc->dev);
2493 unsigned cid = he_mkcid(he_dev, vcc->vpi, vcc->vci);
2525 spin_lock_irqsave(&he_dev->global_lock, flags);
2527 tpd = __alloc_tpd(he_dev);
2534 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2554 tpd->iovec[slot].addr = dma_map_single(&he_dev->pci_dev->dev, skb->data,
2568 __enqueue_tpd(he_dev, tpd, cid);
2569 tpd = __alloc_tpd(he_dev);
2576 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2583 tpd->iovec[slot].addr = skb_frag_dma_map(&he_dev->pci_dev->dev,
2592 tpd->address0 = dma_map_single(&he_dev->pci_dev->dev, skb->data, skb->len, DMA_TO_DEVICE);
2602 __enqueue_tpd(he_dev, tpd, cid);
2603 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2614 struct he_dev *he_dev = HE_DEV(atm_dev);
2627 spin_lock_irqsave(&he_dev->global_lock, flags);
2635 reg.val = he_readl(he_dev, reg.addr);
2639 he_readl_rcm(he_dev, reg.addr);
2643 he_readl_tcm(he_dev, reg.addr);
2647 he_readl_mbox(he_dev, reg.addr);
2653 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2676 struct he_dev *he_dev = HE_DEV(atm_dev);
2680 spin_lock_irqsave(&he_dev->global_lock, flags);
2681 he_writel(he_dev, val, FRAMER + (addr*4));
2682 (void) he_readl(he_dev, FRAMER + (addr*4)); /* flush posted writes */
2683 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2691 struct he_dev *he_dev = HE_DEV(atm_dev);
2694 spin_lock_irqsave(&he_dev->global_lock, flags);
2695 reg = he_readl(he_dev, FRAMER + (addr*4));
2696 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2706 struct he_dev *he_dev = HE_DEV(dev);
2722 he_dev->prod_id, he_dev->media & 0x40 ? "SM" : "MM");
2727 spin_lock_irqsave(&he_dev->global_lock, flags);
2728 mcc += he_readl(he_dev, MCC);
2729 oec += he_readl(he_dev, OEC);
2730 dcc += he_readl(he_dev, DCC);
2731 cec += he_readl(he_dev, CEC);
2732 spin_unlock_irqrestore(&he_dev->global_lock, flags);
2740 CONFIG_IRQ_SIZE, he_dev->irq_peak);
2748 CONFIG_RBRQ_SIZE, he_dev->rbrq_peak);
2752 CONFIG_TBRQ_SIZE, he_dev->tbrq_peak);
2756 rbpl_head = RBPL_MASK(he_readl(he_dev, G0_RBPL_S));
2757 rbpl_tail = RBPL_MASK(he_readl(he_dev, G0_RBPL_T));
2775 he_dev->cs_stper[i].pcr,
2776 he_dev->cs_stper[i].inuse);
2780 he_dev->total_bw, he_dev->atm_dev->link_rate * 10 / 9);
2787 static u8 read_prom_byte(struct he_dev *he_dev, int addr)
2793 val = readl(he_dev->membase + HOST_CNTL);
2798 he_writel(he_dev, val, HOST_CNTL);
2802 he_writel(he_dev, val | readtab[i], HOST_CNTL);
2808 he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);
2810 he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);
2817 he_writel(he_dev, val, HOST_CNTL);
2821 he_writel(he_dev, val | clocktab[j++], HOST_CNTL);
2823 tmp_read = he_readl(he_dev, HOST_CNTL);
2826 he_writel(he_dev, val | clocktab[j++], HOST_CNTL);
2830 he_writel(he_dev, val | ID_CS, HOST_CNTL);