Lines Matching defs:he_writel
176 #define he_writel(dev, val, reg) do { writel(val, (dev)->membase + (reg)); wmb(); } while (0)
185 he_writel(he_dev, val, CON_DAT);
187 he_writel(he_dev, flags | CON_CTL_WRITE | CON_CTL_ADDR(addr), CON_CTL);
203 he_writel(he_dev, flags | CON_CTL_READ | CON_CTL_ADDR(addr), CON_CTL);
455 he_writel(he_dev, lbufd_index, RLBF0_H);
471 he_writel(he_dev, lbufd_index - 2, RLBF0_T);
472 he_writel(he_dev, he_dev->r0_numbuffs, RLBF0_C);
485 he_writel(he_dev, lbufd_index, RLBF1_H);
501 he_writel(he_dev, lbufd_index - 2, RLBF1_T);
502 he_writel(he_dev, he_dev->r1_numbuffs, RLBF1_C);
515 he_writel(he_dev, lbufd_index, TLBF_H);
531 he_writel(he_dev, lbufd_index - 1, TLBF_T);
548 he_writel(he_dev, he_dev->tpdrq_phys, TPDRQ_B_H);
549 he_writel(he_dev, 0, TPDRQ_T);
550 he_writel(he_dev, CONFIG_TPDRQ_SIZE - 1, TPDRQ_S);
776 he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));
777 he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));
778 he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));
779 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
835 he_writel(he_dev, he_dev->rbpl_phys, G0_RBPL_S + (group * 32));
836 he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail),
838 he_writel(he_dev, (CONFIG_RBPL_BUFSIZE - sizeof(struct he_buff))/4,
840 he_writel(he_dev,
857 he_writel(he_dev, he_dev->rbrq_phys, G0_RBRQ_ST + (group * 16));
858 he_writel(he_dev, 0, G0_RBRQ_H + (group * 16));
859 he_writel(he_dev,
864 he_writel(he_dev, RBRQ_TIME(768) | RBRQ_COUNT(7),
867 he_writel(he_dev, RBRQ_TIME(0) | RBRQ_COUNT(1),
882 he_writel(he_dev, he_dev->tbrq_phys, G0_TBRQ_B_T + (group * 16));
883 he_writel(he_dev, 0, G0_TBRQ_H + (group * 16));
884 he_writel(he_dev, CONFIG_TBRQ_SIZE - 1, G0_TBRQ_S + (group * 16));
885 he_writel(he_dev, CONFIG_TBRQ_THRESH, G0_TBRQ_THRESH + (group * 16));
933 he_writel(he_dev, he_dev->irq_phys, IRQ0_BASE);
934 he_writel(he_dev,
937 he_writel(he_dev, IRQ_INT_A | IRQ_TYPE_LINE, IRQ0_CNTL);
938 he_writel(he_dev, 0x0, IRQ0_DATA);
940 he_writel(he_dev, 0x0, IRQ1_BASE);
941 he_writel(he_dev, 0x0, IRQ1_HEAD);
942 he_writel(he_dev, 0x0, IRQ1_CNTL);
943 he_writel(he_dev, 0x0, IRQ1_DATA);
945 he_writel(he_dev, 0x0, IRQ2_BASE);
946 he_writel(he_dev, 0x0, IRQ2_HEAD);
947 he_writel(he_dev, 0x0, IRQ2_CNTL);
948 he_writel(he_dev, 0x0, IRQ2_DATA);
950 he_writel(he_dev, 0x0, IRQ3_BASE);
951 he_writel(he_dev, 0x0, IRQ3_HEAD);
952 he_writel(he_dev, 0x0, IRQ3_CNTL);
953 he_writel(he_dev, 0x0, IRQ3_DATA);
957 he_writel(he_dev, 0x0, GRP_10_MAP);
958 he_writel(he_dev, 0x0, GRP_32_MAP);
959 he_writel(he_dev, 0x0, GRP_54_MAP);
960 he_writel(he_dev, 0x0, GRP_76_MAP);
1057 he_writel(he_dev, 0x0, RESET_CNTL);
1058 he_writel(he_dev, 0xff, RESET_CNTL);
1110 he_writel(he_dev, lb_swap, LB_SWAP);
1113 he_writel(he_dev, he_is622(he_dev) ? LB_64_ENB : 0x0, SDRAM_CTL);
1117 he_writel(he_dev, lb_swap, LB_SWAP);
1126 he_writel(he_dev, host_cntl, HOST_CNTL);
1224 he_writel(he_dev,
1231 he_writel(he_dev, BANK_ON |
1235 he_writel(he_dev,
1238 he_writel(he_dev,
1242 he_writel(he_dev, he_dev->cells_per_lbuf * ATM_CELL_PAYLOAD, LB_CONFIG);
1244 he_writel(he_dev,
1250 he_writel(he_dev, DRF_THRESH(0x20) |
1255 he_writel(he_dev, 0x0, TXAAL5_PROTO);
1257 he_writel(he_dev, PHY_INT_ENB |
1300 he_writel(he_dev, CONFIG_TSRB, TSRB_BA);
1301 he_writel(he_dev, CONFIG_TSRC, TSRC_BA);
1302 he_writel(he_dev, CONFIG_TSRD, TSRD_BA);
1303 he_writel(he_dev, CONFIG_TMABR, TMABR_BA);
1304 he_writel(he_dev, CONFIG_TPDBA, TPD_BA);
1334 he_writel(he_dev, 0x08000, RCMLBM_BA);
1335 he_writel(he_dev, 0x0e000, RCMRSRB_BA);
1336 he_writel(he_dev, 0x0d800, RCMABR_BA);
1343 he_writel(he_dev, 0x0, RLBC_H);
1344 he_writel(he_dev, 0x0, RLBC_T);
1345 he_writel(he_dev, 0x0, RLBC_H2);
1347 he_writel(he_dev, 512, RXTHRSH); /* 10% of r0+r1 buffers */
1348 he_writel(he_dev, 256, LITHRSH); /* 5% of r0+r1 buffers */
1352 he_writel(he_dev, he_is622(he_dev) ? 0x104780 : 0x800, UBUFF_BA);
1357 he_writel(he_dev, 0x000f, G0_INMQ_S);
1358 he_writel(he_dev, 0x200f, G0_INMQ_L);
1360 he_writel(he_dev, 0x001f, G1_INMQ_S);
1361 he_writel(he_dev, 0x201f, G1_INMQ_L);
1363 he_writel(he_dev, 0x002f, G2_INMQ_S);
1364 he_writel(he_dev, 0x202f, G2_INMQ_L);
1366 he_writel(he_dev, 0x003f, G3_INMQ_S);
1367 he_writel(he_dev, 0x203f, G3_INMQ_L);
1369 he_writel(he_dev, 0x004f, G4_INMQ_S);
1370 he_writel(he_dev, 0x204f, G4_INMQ_L);
1372 he_writel(he_dev, 0x005f, G5_INMQ_S);
1373 he_writel(he_dev, 0x205f, G5_INMQ_L);
1375 he_writel(he_dev, 0x006f, G6_INMQ_S);
1376 he_writel(he_dev, 0x206f, G6_INMQ_L);
1378 he_writel(he_dev, 0x007f, G7_INMQ_S);
1379 he_writel(he_dev, 0x207f, G7_INMQ_L);
1381 he_writel(he_dev, 0x0000, G0_INMQ_S);
1382 he_writel(he_dev, 0x0008, G0_INMQ_L);
1384 he_writel(he_dev, 0x0001, G1_INMQ_S);
1385 he_writel(he_dev, 0x0009, G1_INMQ_L);
1387 he_writel(he_dev, 0x0002, G2_INMQ_S);
1388 he_writel(he_dev, 0x000a, G2_INMQ_L);
1390 he_writel(he_dev, 0x0003, G3_INMQ_S);
1391 he_writel(he_dev, 0x000b, G3_INMQ_L);
1393 he_writel(he_dev, 0x0004, G4_INMQ_S);
1394 he_writel(he_dev, 0x000c, G4_INMQ_L);
1396 he_writel(he_dev, 0x0005, G5_INMQ_S);
1397 he_writel(he_dev, 0x000d, G5_INMQ_L);
1399 he_writel(he_dev, 0x0006, G6_INMQ_S);
1400 he_writel(he_dev, 0x000e, G6_INMQ_L);
1402 he_writel(he_dev, 0x0007, G7_INMQ_S);
1403 he_writel(he_dev, 0x000f, G7_INMQ_L);
1408 he_writel(he_dev, 0x0, MCC);
1409 he_writel(he_dev, 0x0, OEC);
1410 he_writel(he_dev, 0x0, DCC);
1411 he_writel(he_dev, 0x0, CEC);
1439 he_writel(he_dev, 0x0, G0_RBPS_S + (group * 32));
1440 he_writel(he_dev, 0x0, G0_RBPS_T + (group * 32));
1441 he_writel(he_dev, 0x0, G0_RBPS_QI + (group * 32));
1442 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
1445 he_writel(he_dev, 0x0, G0_RBPL_S + (group * 32));
1446 he_writel(he_dev, 0x0, G0_RBPL_T + (group * 32));
1447 he_writel(he_dev, RBP_THRESH(0x1) | RBP_QSIZE(0x0),
1449 he_writel(he_dev, 0x0, G0_RBPL_BS + (group * 32));
1451 he_writel(he_dev, 0x0, G0_RBRQ_ST + (group * 16));
1452 he_writel(he_dev, 0x0, G0_RBRQ_H + (group * 16));
1453 he_writel(he_dev, RBRQ_THRESH(0x1) | RBRQ_SIZE(0x0),
1455 he_writel(he_dev, 0x0, G0_RBRQ_I + (group * 16));
1457 he_writel(he_dev, 0x0, G0_TBRQ_B_T + (group * 16));
1458 he_writel(he_dev, 0x0, G0_TBRQ_H + (group * 16));
1459 he_writel(he_dev, TBRQ_THRESH(0x1),
1461 he_writel(he_dev, 0x0, G0_TBRQ_S + (group * 16));
1473 he_writel(he_dev, he_dev->hsp_phys, HSP_BA);
1502 he_writel(he_dev, reg, RC_CONFIG);
1553 he_writel(he_dev, reg, RC_CONFIG);
1794 he_writel(he_dev, RBRQ_MASK(he_dev->rbrq_head),
1875 he_writel(he_dev, TBRQ_MASK(he_dev->tbrq_head),
1924 he_writel(he_dev, RBPL_MASK(he_dev->rbpl_tail), G0_RBPL_T);
2005 he_writel(he_dev,
2044 he_writel(he_dev, INT_CLEAR_A, INT_FIFO); /* clear interrupt */
2113 he_writel(he_dev, TPDRQ_MASK(he_dev->tpdrq_tail), TPDRQ_T);
2681 he_writel(he_dev, val, FRAMER + (addr*4));
2798 he_writel(he_dev, val, HOST_CNTL);
2802 he_writel(he_dev, val | readtab[i], HOST_CNTL);
2808 he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);
2810 he_writel(he_dev, val | clocktab[j++] | (((addr >> i) & 1) << 9), HOST_CNTL);
2817 he_writel(he_dev, val, HOST_CNTL);
2821 he_writel(he_dev, val | clocktab[j++], HOST_CNTL);
2826 he_writel(he_dev, val | clocktab[j++], HOST_CNTL);
2830 he_writel(he_dev, val | ID_CS, HOST_CNTL);