Lines Matching defs:eni_in
154 #define eni_in(r) readl(eni_dev->reg+(r)*4)
316 eni_out(eni_in(MID_MC_S) &
452 dma_wr = eni_in(MID_DMA_WR_RX);
453 dma_rd = eni_in(MID_DMA_RD_RX);
684 while (eni_in(MID_SERV_WRITE) != eni_dev->serv_read) {
916 eni_dev->serv_read = eni_in(MID_SERV_WRITE);
1088 eni_in(MID_TX_RDPTR(tx->index)),tx->words)) {
1094 dma_wr = eni_in(MID_DMA_WR_TX);
1095 dma_rd = eni_in(MID_DMA_RD_TX);
1222 (unsigned) eni_in(MID_TX_DESCRSTART(tx->index)));
1224 eni_in(MID_TX_DESCRSTART(tx->index))) {
1337 tx->tx_pos = eni_in(MID_TX_DESCRSTART(tx->index)) &
1422 while (eni_in(MID_TX_RDPTR(eni_vcc->tx->index)) !=
1423 eni_in(MID_TX_DESCRSTART(eni_vcc->tx->index)))
1499 reason = eni_in(MID_ISA);
1509 eni_dev->lost += eni_in(MID_STAT) & MID_OVFL_TRASH;
1767 if (!(eni_in(MID_RES_ID_MCON) & 0x200) != !eni_dev->asic) {
1770 dev->number,(unsigned) eni_in(MID_RES_ID_MCON));
1781 eni_in(MID_RES_ID_MCON) & 0x200 ? "ASIC" : "FPGA",
1782 media_name[eni_in(MID_RES_ID_MCON) & DAUGHTER_ID]);
1876 eni_out(eni_in(MID_MC_S) | (1 << MID_INT_SEL_SHIFT) |
1880 (void) eni_in(MID_ISA); /* clear Midway interrupts */