Lines Matching refs:mmio
442 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
453 mmio += PDC_CHIP0_OFS;
491 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
495 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
502 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
510 mmio += PDC_CHIP0_OFS;
526 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
530 VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
555 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
558 mmio += PDC_CHIP0_OFS;
560 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
561 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
563 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
564 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
628 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
634 mmio += PDC_CHIP0_OFS;
653 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
654 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
691 void __iomem *mmio)
707 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
718 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
733 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
736 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
737 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
746 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
841 void __iomem *mmio = ap->ioaddr.cmd_addr;
846 tmp = readl(mmio + PDC_CTLSTAT);
849 writel(tmp, mmio + PDC_CTLSTAT);
850 readl(mmio + PDC_CTLSTAT); /* flush */
855 void __iomem *mmio = ap->ioaddr.cmd_addr;
864 tmp = readl(mmio + PDC_CTLSTAT);
866 writel(tmp, mmio + PDC_CTLSTAT);
867 readl(mmio + PDC_CTLSTAT); /* flush */
872 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
879 tmp = readl(mmio);
886 writel(tmp, mmio);
890 writel(tmp, mmio);
891 readl(mmio); /* flush */
990 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
994 mmio += PDC_CHIP0_OFS;
1000 writel(0x01, mmio + PDC_GENERAL_CTLR);
1001 readl(mmio + PDC_GENERAL_CTLR);
1002 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1003 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1014 writel(0x01, mmio + PDC_GENERAL_CTLR);
1015 readl(mmio + PDC_GENERAL_CTLR);
1016 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1017 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1025 writel(0x01, mmio + PDC_GENERAL_CTLR);
1026 readl(mmio + PDC_GENERAL_CTLR);
1027 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1028 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1042 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1046 mmio += PDC_CHIP0_OFS;
1052 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1053 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1059 writel(0x01, mmio + PDC_GENERAL_CTLR);
1060 readl(mmio + PDC_GENERAL_CTLR);
1065 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1066 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1068 writel(0x01, mmio + PDC_GENERAL_CTLR);
1069 readl(mmio + PDC_GENERAL_CTLR);
1076 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1077 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1079 writel(0x01, mmio + PDC_GENERAL_CTLR);
1080 readl(mmio + PDC_GENERAL_CTLR);
1088 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1094 mmio += PDC_CHIP0_OFS;
1100 writel(i2creg, mmio + PDC_I2C_ADDR_DATA);
1101 readl(mmio + PDC_I2C_ADDR_DATA);
1105 mmio + PDC_I2C_CONTROL);
1108 status = readl(mmio + PDC_I2C_CONTROL);
1110 status = readl(mmio + PDC_I2C_ADDR_DATA);
1147 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1167 mmio += PDC_CHIP0_OFS;
1200 writel(data, mmio + PDC_DIMM0_CONTROL);
1201 readl(mmio + PDC_DIMM0_CONTROL);
1210 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1213 mmio += PDC_CHIP0_OFS;
1223 writel(data, mmio + PDC_SDRAM_CONTROL);
1224 readl(mmio + PDC_SDRAM_CONTROL);
1235 writel(data, mmio + PDC_SDRAM_CONTROL);
1236 readl(mmio + PDC_SDRAM_CONTROL);
1243 writel(data, mmio + PDC_SDRAM_CONTROL);
1247 data = readl(mmio + PDC_SDRAM_CONTROL);
1267 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1270 mmio += PDC_CHIP0_OFS;
1275 writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1276 time_period = readl(mmio + PDC_TIME_PERIOD);
1280 writel(PDC_TIMER_DEFAULT, mmio + PDC_TIME_CONTROL);
1281 readl(mmio + PDC_TIME_CONTROL);
1291 tcount = readl(mmio + PDC_TIME_COUNTER);
1319 writel(pci_status, mmio + PDC_CTL_STATUS);
1320 readl(mmio + PDC_CTL_STATUS);
1402 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1405 mmio += PDC_CHIP0_OFS;
1410 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1412 writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1417 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1419 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1420 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1424 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1426 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1427 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1469 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");