Lines Matching defs:base
152 void __iomem *base;
159 void __iomem *base = priv->base;
162 iowrite32(0, base + SATAPHYADDR_REG);
164 iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG);
167 iowrite32(0, base + SATAPHYRESET_REG);
173 void __iomem *base = priv->base;
177 iowrite32(0, base + SATAPHYRESET_REG);
179 iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG);
181 iowrite32(val, base + SATAPHYWDATA_REG);
186 iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG);
189 val = ioread32(base + SATAPHYACK_REG);
196 iowrite32(0, base + SATAPHYADDR_REG);
212 void __iomem *base = priv->base;
214 iowrite32(RCAR_GEN2_PHY_CTL1, base + RCAR_GEN2_PHY_CTL1_REG);
215 iowrite32(RCAR_GEN2_PHY_CTL2, base + RCAR_GEN2_PHY_CTL2_REG);
216 iowrite32(RCAR_GEN2_PHY_CTL3, base + RCAR_GEN2_PHY_CTL3_REG);
217 iowrite32(RCAR_GEN2_PHY_CTL4, base + RCAR_GEN2_PHY_CTL4_REG);
219 RCAR_GEN2_PHY_CTL5_TR, base + RCAR_GEN2_PHY_CTL5_REG);
227 iowrite32(priv->sataint_mask, priv->base + SATAINTMASK_REG);
235 void __iomem *base = priv->base;
238 iowrite32(~(u32)SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG);
243 iowrite32(priv->sataint_mask & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG);
568 void __iomem *base = priv->base;
573 iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG);
576 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
584 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
594 void __iomem *base = priv->base;
598 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
601 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
608 void __iomem *base = priv->base;
612 dmactl = ioread32(base + ATAPI_CONTROL1_REG);
616 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
629 status = ioread32(priv->base + ATAPI_STATUS_REG);
684 serror = ioread32(priv->base + SCRSERR_REG);
726 void __iomem *base = priv->base;
734 sataintstat = ioread32(base + SATAINTSTAT_REG);
739 iowrite32(~sataintstat & priv->sataint_mask, base + SATAINTSTAT_REG);
761 void __iomem *base = priv->base;
771 ioaddr->cmd_addr = base + SDATA_REG;
772 ioaddr->ctl_addr = base + SSDEVCON_REG;
773 ioaddr->scr_addr = base + SCRSSTS_REG;
790 void __iomem *base = priv->base;
794 val = ioread32(base + ATAPI_CONTROL1_REG);
796 iowrite32(val, base + ATAPI_CONTROL1_REG);
799 val = ioread32(base + ATAPI_CONTROL1_REG);
803 iowrite32(val, base + ATAPI_CONTROL1_REG);
806 val = ioread32(base + ATAPI_CONTROL1_REG);
808 iowrite32(val, base + ATAPI_CONTROL1_REG);
811 iowrite32(0, base + SATAINTSTAT_REG);
812 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG);
815 iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
921 priv->base = devm_ioremap_resource(dev, mem);
922 if (IS_ERR(priv->base)) {
923 ret = PTR_ERR(priv->base);
948 void __iomem *base = priv->base;
953 iowrite32(0, base + ATAPI_INT_ENABLE_REG);
955 iowrite32(0, base + SATAINTSTAT_REG);
956 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG);
969 void __iomem *base = priv->base;
975 iowrite32(0, base + ATAPI_INT_ENABLE_REG);
977 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG);
989 void __iomem *base = priv->base;
1002 iowrite32(0, base + SATAINTSTAT_REG);
1003 iowrite32(priv->sataint_mask, base + SATAINTMASK_REG);
1007 base + ATAPI_INT_ENABLE_REG);