Lines Matching defs:mmio_base
192 u8 __iomem *mmio_base = qs_mmio_base(ap->host);
194 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
200 u8 __iomem *mmio_base = qs_mmio_base(ap->host);
203 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
361 u8 __iomem *mmio_base = qs_mmio_base(host);
364 u32 sff0 = readl(mmio_base + QS_HST_SFF);
365 u32 sff1 = readl(mmio_base + QS_HST_SFF + 4);
471 void __iomem *mmio_base = qs_mmio_base(ap->host);
472 void __iomem *chan = mmio_base + (ap->port_no * 0x4000);
493 void __iomem *mmio_base = qs_mmio_base(host);
495 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
496 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
501 void __iomem *mmio_base = host->iomap[QS_MMIO_BAR];
504 writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */
505 writeb(QS_CNFG3_GSRST, mmio_base + QS_HCF_CNFG3); /* global reset */
509 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
514 writeb(QS_SERD3_PHY_ENA, mmio_base + QS_HVS_SERD3); /* enable phy */
517 u8 __iomem *chan = mmio_base + (port_no * 0x4000);
526 writeb(1, mmio_base + QS_HCT_CTRL); /* enable host interrupts */
539 static int qs_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
541 u32 bus_info = readl(mmio_base + QS_HID_HPHY);