Lines Matching defs:tmp
593 u16 tmp, status;
609 tmp = readw(mmio + NV_ADMA_CTL);
610 writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
631 u16 tmp, status;
639 tmp = readw(mmio + NV_ADMA_CTL);
640 writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);
1009 u16 tmp;
1021 tmp = readw(mmio + NV_ADMA_CTL);
1022 writew(tmp & ~(NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
1031 u16 tmp;
1039 tmp = readw(mmio + NV_ADMA_CTL);
1040 writew(tmp | (NV_ADMA_CTL_AIEN | NV_ADMA_CTL_HOTPLUG_IEN),
1095 u16 tmp;
1168 tmp = readw(mmio + NV_ADMA_CTL);
1169 writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
1172 tmp = readw(mmio + NV_ADMA_CTL);
1173 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1176 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1213 u16 tmp;
1229 tmp = readw(mmio + NV_ADMA_CTL);
1230 writew((tmp & ~NV_ADMA_CTL_GO) | NV_ADMA_CTL_AIEN |
1233 tmp = readw(mmio + NV_ADMA_CTL);
1234 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1237 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1640 u16 tmp;
1679 tmp = readw(mmio + NV_ADMA_CTL);
1680 writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1683 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1819 u32 tmp;
1828 tmp = readl(mmio + NV_CTL_MCP55);
1829 tmp &= ~(NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ);
1830 writel(tmp, mmio + NV_CTL_MCP55);
1838 u32 tmp;
1847 tmp = readl(mmio + NV_CTL_MCP55);
1848 writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55);
1856 u32 tmp;
1867 tmp = readl(mmio + NV_CTL_MCP55);
1868 VPRINTK("HOST_CTL:0x%X\n", tmp);
1869 writel(tmp | NV_CTL_PRI_SWNCQ | NV_CTL_SEC_SWNCQ, mmio + NV_CTL_MCP55);
1872 tmp = readl(mmio + NV_INT_ENABLE_MCP55);
1873 VPRINTK("HOST_ENABLE:0x%X\n", tmp);
1874 writel(tmp | 0x00fd00fd, mmio + NV_INT_ENABLE_MCP55);