Lines Matching refs:hpriv
438 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
439 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
440 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
441 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
442 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
577 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
579 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
580 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
582 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
584 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
604 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
606 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
607 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
609 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
611 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
614 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
616 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
617 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
619 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
621 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
622 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
624 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
626 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
628 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
631 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
634 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
918 struct mv_host_priv *hpriv = host->private_data;
919 return hpriv->base;
989 struct mv_host_priv *hpriv,
1019 static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
1033 writelfl(mask, hpriv->main_irq_mask_addr);
1039 struct mv_host_priv *hpriv = host->private_data;
1042 old_mask = hpriv->main_irq_mask;
1045 hpriv->main_irq_mask = new_mask;
1046 mv_write_main_irq_mask(new_mask, hpriv);
1067 struct mv_host_priv *hpriv = ap->host->private_data;
1081 if (IS_GEN_IIE(hpriv))
1090 struct mv_host_priv *hpriv = host->private_data;
1091 void __iomem *mmio = hpriv->base, *hc_mmio;
1094 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
1113 if (is_dual_hc && !IS_GEN_I(hpriv)) {
1171 struct mv_host_priv *hpriv = ap->host->private_data;
1175 mv_set_edma_ptrs(port_mmio, hpriv, pp);
1362 struct mv_host_priv *hpriv = link->ap->host->private_data;
1380 if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) {
1509 struct mv_host_priv *hpriv = ap->host->private_data;
1513 old = readl(hpriv->base + GPIO_PORT_CTL);
1519 writel(new, hpriv->base + GPIO_PORT_CTL);
1563 struct mv_host_priv *hpriv = host->private_data;
1567 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1569 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1578 struct mv_host_priv *hpriv = host->private_data;
1583 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1587 for (port = 0; port < hpriv->n_ports; port++) {
1595 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1605 struct mv_host_priv *hpriv = ap->host->private_data;
1613 if (IS_GEN_I(hpriv))
1616 else if (IS_GEN_II(hpriv)) {
1620 } else if (IS_GEN_IIE(hpriv)) {
1642 if (!IS_SOC(hpriv))
1645 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1649 if (IS_SOC(hpriv)) {
1667 struct mv_host_priv *hpriv = ap->host->private_data;
1672 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1676 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1685 if (tag == 0 || !IS_GEN_I(hpriv))
1686 dma_pool_free(hpriv->sg_tbl_pool,
1707 struct mv_host_priv *hpriv = ap->host->private_data;
1717 pp->crqb = dma_pool_zalloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1721 pp->crpb = dma_pool_zalloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1726 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1733 if (tag == 0 || !IS_GEN_I(hpriv)) {
1734 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
2403 struct mv_host_priv *hpriv = ap->host->private_data;
2415 if (IS_GEN_II(hpriv))
2642 struct mv_host_priv *hpriv = ap->host->private_data;
2657 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2677 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2714 if (IS_GEN_I(hpriv)) {
2802 struct mv_host_priv *hpriv = ap->host->private_data;
2819 if (IS_GEN_I(hpriv)) {
2885 struct mv_host_priv *hpriv = host->private_data;
2886 void __iomem *mmio = hpriv->base, *hc_mmio;
2893 for (port = 0; port < hpriv->n_ports; port++) {
2928 if ((port + p) >= hpriv->n_ports)
2950 struct mv_host_priv *hpriv = host->private_data;
2957 err_cause = readl(mmio + hpriv->irq_cause_offset);
2964 writelfl(0, mmio + hpriv->irq_cause_offset);
3005 struct mv_host_priv *hpriv = host->private_data;
3007 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
3014 mv_write_main_irq_mask(0, hpriv);
3016 main_irq_cause = readl(hpriv->main_irq_cause_addr);
3017 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
3023 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
3024 handled = mv_pci_error(host, hpriv->base);
3031 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
3057 struct mv_host_priv *hpriv = link->ap->host->private_data;
3058 void __iomem *mmio = hpriv->base;
3071 struct mv_host_priv *hpriv = link->ap->host->private_data;
3072 void __iomem *mmio = hpriv->base;
3099 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3104 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
3112 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3113 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
3116 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3129 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3135 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
3150 tmp |= hpriv->signal[port].pre;
3151 tmp |= hpriv->signal[port].amps;
3158 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
3163 mv_reset_channel(hpriv, mmio, port);
3182 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3200 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3207 mv5_reset_hc_port(hpriv, mmio,
3210 mv5_reset_one_hc(hpriv, mmio, hc);
3220 struct mv_host_priv *hpriv = host->private_data;
3231 ZERO(hpriv->irq_cause_offset);
3232 ZERO(hpriv->irq_mask_offset);
3240 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3244 mv5_reset_flash(hpriv, mmio);
3261 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3316 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
3324 hpriv->signal[idx].amps = 0x7 << 8;
3325 hpriv->signal[idx].pre = 0x1 << 5;
3332 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3333 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3336 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
3341 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3346 u32 hp_flags = hpriv->hp_flags;
3376 if (IS_SOC(hpriv))
3386 if (IS_GEN_IIE(hpriv))
3404 m2 |= hpriv->signal[port].amps;
3405 m2 |= hpriv->signal[port].pre;
3409 if (IS_GEN_IIE(hpriv)) {
3419 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3425 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3434 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3435 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3440 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3445 mv_reset_channel(hpriv, mmio, port);
3465 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3478 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3483 for (port = 0; port < hpriv->n_ports; port++)
3484 mv_soc_reset_hc_port(hpriv, mmio, port);
3486 mv_soc_reset_one_hc(hpriv, mmio);
3491 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3502 static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
3540 static bool soc_is_65n(struct mv_host_priv *hpriv)
3542 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3559 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
3572 if (!IS_GEN_I(hpriv)) {
3585 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3587 if (IS_GEN_I(hpriv))
3623 struct mv_host_priv *hpriv = ap->host->private_data;
3625 void __iomem *mmio = hpriv->base;
3630 mv_reset_channel(hpriv, mmio, ap->port_no);
3646 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3667 struct mv_host_priv *hpriv = ap->host->private_data;
3670 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3731 struct mv_host_priv *hpriv = host->private_data;
3732 void __iomem *mmio = hpriv->base;
3735 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
3745 struct mv_host_priv *hpriv = host->private_data;
3746 void __iomem *mmio = hpriv->base;
3759 struct mv_host_priv *hpriv = host->private_data;
3760 void __iomem *mmio = hpriv->base;
3772 struct mv_host_priv *hpriv = host->private_data;
3773 u32 hp_flags = hpriv->hp_flags;
3777 hpriv->ops = &mv5xxx_ops;
3797 hpriv->ops = &mv5xxx_ops;
3817 hpriv->ops = &mv6xxx_ops;
3869 hpriv->ops = &mv6xxx_ops;
3886 if (soc_is_65n(hpriv))
3887 hpriv->ops = &mv_soc_65n_ops;
3889 hpriv->ops = &mv_soc_ops;
3899 hpriv->hp_flags = hp_flags;
3901 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
3902 hpriv->irq_mask_offset = PCIE_IRQ_MASK;
3903 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3905 hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
3906 hpriv->irq_mask_offset = PCI_IRQ_MASK;
3907 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3926 struct mv_host_priv *hpriv = host->private_data;
3927 void __iomem *mmio = hpriv->base;
3929 rc = mv_chip_id(host, hpriv->board_idx);
3933 if (IS_SOC(hpriv)) {
3934 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
3935 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
3937 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
3938 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
3942 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3950 if (hpriv->ops->read_preamp)
3951 hpriv->ops->read_preamp(hpriv, port, mmio);
3953 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3957 hpriv->ops->reset_flash(hpriv, mmio);
3958 hpriv->ops->reset_bus(host, mmio);
3959 hpriv->ops->enable_leds(hpriv, mmio);
3980 if (!IS_SOC(hpriv)) {
3982 writelfl(0, mmio + hpriv->irq_cause_offset);
3985 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
3999 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
4001 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
4003 if (!hpriv->crqb_pool)
4006 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
4008 if (!hpriv->crpb_pool)
4011 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
4013 if (!hpriv->sg_tbl_pool)
4019 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
4025 writel(0, hpriv->base + WINDOW_CTRL(i));
4026 writel(0, hpriv->base + WINDOW_BASE(i));
4035 hpriv->base + WINDOW_CTRL(i));
4036 writel(cs->base, hpriv->base + WINDOW_BASE(i));
4055 struct mv_host_priv *hpriv;
4106 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4108 if (!host || !hpriv)
4110 hpriv->port_clks = devm_kcalloc(&pdev->dev,
4113 if (!hpriv->port_clks)
4115 hpriv->port_phys = devm_kcalloc(&pdev->dev,
4118 if (!hpriv->port_phys)
4120 host->private_data = hpriv;
4121 hpriv->board_idx = chip_soc;
4124 hpriv->base = devm_ioremap(&pdev->dev, res->start,
4126 if (!hpriv->base)
4129 hpriv->base -= SATAHC0_REG_BASE;
4131 hpriv->clk = clk_get(&pdev->dev, NULL);
4132 if (IS_ERR(hpriv->clk))
4135 clk_prepare_enable(hpriv->clk);
4140 hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);
4141 if (!IS_ERR(hpriv->port_clks[port]))
4142 clk_prepare_enable(hpriv->port_clks[port]);
4145 hpriv->port_phys[port] = devm_phy_optional_get(&pdev->dev,
4147 if (IS_ERR(hpriv->port_phys[port])) {
4148 rc = PTR_ERR(hpriv->port_phys[port]);
4149 hpriv->port_phys[port] = NULL;
4154 hpriv->n_ports = port;
4157 phy_power_on(hpriv->port_phys[port]);
4161 hpriv->n_ports = n_ports;
4168 mv_conf_mbus_windows(hpriv, dram);
4170 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4181 hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL;
4196 if (!IS_ERR(hpriv->clk)) {
4197 clk_disable_unprepare(hpriv->clk);
4198 clk_put(hpriv->clk);
4200 for (port = 0; port < hpriv->n_ports; port++) {
4201 if (!IS_ERR(hpriv->port_clks[port])) {
4202 clk_disable_unprepare(hpriv->port_clks[port]);
4203 clk_put(hpriv->port_clks[port]);
4205 phy_power_off(hpriv->port_phys[port]);
4222 struct mv_host_priv *hpriv = host->private_data;
4226 if (!IS_ERR(hpriv->clk)) {
4227 clk_disable_unprepare(hpriv->clk);
4228 clk_put(hpriv->clk);
4231 if (!IS_ERR(hpriv->port_clks[port])) {
4232 clk_disable_unprepare(hpriv->port_clks[port]);
4233 clk_put(hpriv->port_clks[port]);
4235 phy_power_off(hpriv->port_phys[port]);
4257 struct mv_host_priv *hpriv = host->private_data;
4264 mv_conf_mbus_windows(hpriv, dram);
4335 struct mv_host_priv *hpriv = host->private_data;
4350 if (IS_GEN_I(hpriv))
4352 else if (IS_GEN_II(hpriv))
4354 else if (IS_GEN_IIE(hpriv))
4361 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
4378 struct mv_host_priv *hpriv;
4387 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4388 if (!host || !hpriv)
4390 host->private_data = hpriv;
4391 hpriv->n_ports = n_ports;
4392 hpriv->board_idx = board_idx;
4405 hpriv->base = host->iomap[MV_PRIMARY_BAR];
4413 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4419 void __iomem *port_mmio = mv_port_base(hpriv->base, port);
4420 unsigned int offset = port_mmio - hpriv->base;
4433 hpriv->hp_flags |= MV_HP_FLAG_MSI;
4441 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);