Lines Matching defs:tmp
1824 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1826 *cmdw = cpu_to_le16(tmp);
3091 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3092 tmp |= (1 << 0);
3093 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3108 u32 tmp;
3110 tmp = readl(phy_mmio + MV5_PHY_MODE);
3112 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3113 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
3118 u32 tmp;
3124 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3125 tmp |= ~(1 << 0);
3126 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3134 u32 tmp;
3138 tmp = readl(phy_mmio + MV5_LTMODE);
3139 tmp |= (1 << 19);
3140 writel(tmp, phy_mmio + MV5_LTMODE);
3142 tmp = readl(phy_mmio + MV5_PHY_CTL);
3143 tmp &= ~0x3;
3144 tmp |= 0x1;
3145 writel(tmp, phy_mmio + MV5_PHY_CTL);
3148 tmp = readl(phy_mmio + MV5_PHY_MODE);
3149 tmp &= ~mask;
3150 tmp |= hpriv->signal[port].pre;
3151 tmp |= hpriv->signal[port].amps;
3152 writel(tmp, phy_mmio + MV5_PHY_MODE);
3186 u32 tmp;
3193 tmp = readl(hc_mmio + 0x20);
3194 tmp &= 0x1c1c1c1c;
3195 tmp |= 0x03030303;
3196 writel(tmp, hc_mmio + 0x20);
3221 u32 tmp;
3223 tmp = readl(mmio + MV_PCI_MODE);
3224 tmp &= 0xff00ffff;
3225 writel(tmp, mmio + MV_PCI_MODE);
3242 u32 tmp;
3246 tmp = readl(mmio + GPIO_PORT_CTL);
3247 tmp &= 0x3;
3248 tmp |= (1 << 5) | (1 << 6);
3249 writel(tmp, mmio + GPIO_PORT_CTL);
3320 u32 tmp;
3322 tmp = readl(mmio + RESET_CFG);
3323 if ((tmp & (1 << 0)) == 0) {
3330 tmp = readl(port_mmio + PHY_MODE2);
3332 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3333 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3429 u32 tmp;
3432 tmp = readl(port_mmio + PHY_MODE2);
3434 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3435 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */