Lines Matching defs:port

144 	/* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
147 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
214 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
215 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
237 DMA_IRQ = (1 << 0), /* shift by port # */
239 DEV_IRQ = (1 << 8), /* shift by port # */
505 * We keep a local cache of a few frequently accessed port
578 unsigned int port);
605 unsigned int port);
615 unsigned int port);
632 void __iomem *mmio, unsigned int port);
862 static inline unsigned int mv_hc_from_port(unsigned int port)
864 return port >> MV_PORT_HC_SHIFT;
867 static inline unsigned int mv_hardport_from_port(unsigned int port)
869 return port & MV_PORT_MASK;
877 * port is the sole input, in range 0..7.
881 * Note that port and hardport may be the same variable in some cases.
883 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
885 shift = mv_hc_from_port(port) * HC_SHIFT; \
886 hardport = mv_hardport_from_port(port); \
896 unsigned int port)
898 return mv_hc_base(base, mv_hc_from_port(port));
901 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
903 return mv_hc_base_from_port(base, port) +
905 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
908 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
910 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
911 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
933 * mv_save_cached_regs - (re-)initialize cached port registers
934 * @ap: the port whose registers we are caching
936 * Initialize the local cache of port registers,
954 * mv_write_cached_reg - write to a cached port register
1024 * and the corresponding individual port DONE_IRQ bits.
1053 unsigned int shift, hardport, port = ap->port_no;
1056 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1151 * @base: port base address
1152 * @pp: port private data
1280 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1285 port >> MV_PORT_HC_SHIFT);
1289 if (0 > port) {
1291 num_ports = 8; /* shld be benign for 4 port devs */
1294 start_hc = port >> MV_PORT_HC_SHIFT;
1295 start_port = port;
1298 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1317 DPRINTK("EDMA regs (port %i):\n", p);
1319 DPRINTK("SATA regs (port %i):\n", p);
1410 * Gen-II does not support NCQ over a port multiplier
1454 * If the port is completely idle, then allow the new qc.
1460 * The port is operating in host queuing mode (EDMA) with NCQ
1553 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1581 unsigned int port;
1587 for (port = 0; port < hpriv->n_ports; port++) {
1588 struct ata_port *this_ap = host->ports[port];
1698 * Allocate and point to DMA memory, init port private memory,
1760 * Stop DMA, cleanup port memory.
1952 * @ap: port for which to retrieve DMA status.
2197 * @ap: ATA port to fetch status from
2254 /* Restore original port configuration */
2395 * port. Turn off EDMA so there won't be problems accessing
2442 * before we freeze the port entirely.
2512 * Set a port flag to prevent further I/O being enqueued.
2513 * Leave the EDMA running to drain outstanding commands from this port.
2626 * mv_err_intr - Handle error interrupts on the port
2631 * Also, if the port disabled DMA, update our cached copy to match.
2848 * so that we have a consistent view for this port,
2887 unsigned int handled = 0, port;
2893 for (port = 0; port < hpriv->n_ports; port++) {
2894 struct ata_port *ap = host->ports[port];
2897 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2902 if (hardport == 0) { /* first port on this hc ? */
2909 port += MV_PORTS_PER_HC - 1;
2928 if ((port + p) >= hpriv->n_ports)
2934 hc_mmio = mv_hc_base_from_port(mmio, port);
2939 * Handle interrupts signalled for this port:
3130 unsigned int port)
3132 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
3150 tmp |= hpriv->signal[port].pre;
3151 tmp |= hpriv->signal[port].amps;
3159 unsigned int port)
3161 void __iomem *port_mmio = mv_port_base(mmio, port);
3163 mv_reset_channel(hpriv, mmio, port);
3203 unsigned int hc, port;
3206 for (port = 0; port < MV_PORTS_PER_HC; port++)
3208 (hc * MV_PORTS_PER_HC) + port);
3342 unsigned int port)
3344 void __iomem *port_mmio = mv_port_base(mmio, port);
3404 m2 |= hpriv->signal[port].amps;
3405 m2 |= hpriv->signal[port].pre;
3441 void __iomem *mmio, unsigned int port)
3443 void __iomem *port_mmio = mv_port_base(mmio, port);
3445 mv_reset_channel(hpriv, mmio, port);
3481 unsigned int port;
3483 for (port = 0; port < hpriv->n_ports; port++)
3484 mv_soc_reset_hc_port(hpriv, mmio, port);
3503 void __iomem *mmio, unsigned int port)
3505 void __iomem *port_mmio = mv_port_base(mmio, port);
3668 unsigned int port = ap->port_no;
3669 unsigned int hardport = mv_hardport_from_port(port);
3670 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3674 /* clear EDMA errors on this port */
3685 * mv_port_init - Perform some early initialization on a single port.
3686 * @port: libata data structure storing shadow register addresses
3687 * @port_mmio: base address of the port
3690 * interrupts on the port, and unmask interrupts for the future
3691 * start of the port.
3696 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
3702 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
3703 port->error_addr =
3704 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3705 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3706 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3707 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3708 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3709 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
3710 port->status_addr =
3711 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3713 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
3715 /* Clear any currently outstanding port interrupt conditions */
3918 * our port init and clear/unmask all/relevant host interrupts.
3925 int rc = 0, n_hc, port, hc;
3949 for (port = 0; port < host->n_ports; port++)
3951 hpriv->ops->read_preamp(hpriv, port, mmio);
3961 for (port = 0; port < host->n_ports; port++) {
3962 struct ata_port *ap = host->ports[port];
3963 void __iomem *port_mmio = mv_port_base(mmio, port);
3990 * The per-port interrupts get done later as ports are set up.
4059 int port;
4137 for (port = 0; port < n_ports; port++) {
4139 sprintf(port_number, "%d", port);
4140 hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);
4141 if (!IS_ERR(hpriv->port_clks[port]))
4142 clk_prepare_enable(hpriv->port_clks[port]);
4144 sprintf(port_number, "port%d", port);
4145 hpriv->port_phys[port] = devm_phy_optional_get(&pdev->dev,
4147 if (IS_ERR(hpriv->port_phys[port])) {
4148 rc = PTR_ERR(hpriv->port_phys[port]);
4149 hpriv->port_phys[port] = NULL;
4154 hpriv->n_ports = port;
4157 phy_power_on(hpriv->port_phys[port]);
4200 for (port = 0; port < hpriv->n_ports; port++) {
4201 if (!IS_ERR(hpriv->port_clks[port])) {
4202 clk_disable_unprepare(hpriv->port_clks[port]);
4203 clk_put(hpriv->port_clks[port]);
4205 phy_power_off(hpriv->port_phys[port]);
4223 int port;
4230 for (port = 0; port < host->n_ports; port++) {
4231 if (!IS_ERR(hpriv->port_clks[port])) {
4232 clk_disable_unprepare(hpriv->port_clks[port]);
4233 clk_put(hpriv->port_clks[port]);
4235 phy_power_off(hpriv->port_phys[port]);
4379 int n_ports, port, rc;
4417 for (port = 0; port < host->n_ports; port++) {
4418 struct ata_port *ap = host->ports[port];
4419 void __iomem *port_mmio = mv_port_base(hpriv->base, port);
4423 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");