Lines Matching defs:host
284 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
585 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
612 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
630 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
633 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
916 static inline void __iomem *mv_host_base(struct ata_host *host)
918 struct mv_host_priv *hpriv = host->private_data;
924 return mv_port_base(mv_host_base(ap->host), ap->port_no);
1036 static void mv_set_main_irq_mask(struct ata_host *host,
1039 struct mv_host_priv *hpriv = host->private_data;
1060 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
1067 struct mv_host_priv *hpriv = ap->host->private_data;
1070 mv_host_base(ap->host), ap->port_no);
1087 static void mv_set_irq_coalescing(struct ata_host *host,
1090 struct mv_host_priv *hpriv = host->private_data;
1110 spin_lock_irqsave(&host->lock, flags);
1111 mv_set_main_irq_mask(host, coal_disable, 0);
1115 * GEN_II/GEN_IIE with dual host controllers:
1145 mv_set_main_irq_mask(host, 0, coal_enable);
1146 spin_unlock_irqrestore(&host->lock, flags);
1171 struct mv_host_priv *hpriv = ap->host->private_data;
1362 struct mv_host_priv *hpriv = link->ap->host->private_data;
1460 * The port is operating in host queuing mode (EDMA) with NCQ
1509 struct mv_host_priv *hpriv = ap->host->private_data;
1562 struct ata_host *host = ap->host;
1563 struct mv_host_priv *hpriv = host->private_data;
1570 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1577 struct ata_host *host = ap->host;
1578 struct mv_host_priv *hpriv = host->private_data;
1588 struct ata_port *this_ap = host->ports[port];
1596 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
1605 struct mv_host_priv *hpriv = ap->host->private_data;
1641 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1667 struct mv_host_priv *hpriv = ap->host->private_data;
1706 struct device *dev = ap->host->dev;
1707 struct mv_host_priv *hpriv = ap->host->private_data;
1763 * This routine uses the host lock to protect the DMA stop.
1916 /* start host DMA transaction */
2321 * mv_qc_issue - Initiate a command to the host
2403 struct mv_host_priv *hpriv = ap->host->private_data;
2642 struct mv_host_priv *hpriv = ap->host->private_data;
2802 struct mv_host_priv *hpriv = ap->host->private_data;
2876 * mv_host_intr - Handle all interrupts on the given host controller
2877 * @host: host specific structure
2883 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2885 struct mv_host_priv *hpriv = host->private_data;
2894 struct ata_port *ap = host->ports[port];
2899 * Each hc within the host has its own hc_irq_cause register,
2948 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2950 struct mv_host_priv *hpriv = host->private_data;
2959 dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause);
2962 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2966 for (i = 0; i < host->n_ports; i++) {
2967 ap = host->ports[i];
2991 * @dev_instance: private data; in this case the host structure
2993 * Read the read only register to determine if any host
2999 * This routine holds the host lock while processing pending
3004 struct ata_host *host = dev_instance;
3005 struct mv_host_priv *hpriv = host->private_data;
3010 spin_lock(&host->lock);
3024 handled = mv_pci_error(host, hpriv->base);
3026 handled = mv_host_intr(host, pending_irqs);
3033 spin_unlock(&host->lock);
3057 struct mv_host_priv *hpriv = link->ap->host->private_data;
3071 struct mv_host_priv *hpriv = link->ap->host->private_data;
3083 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
3085 struct pci_dev *pdev = to_pci_dev(host->dev);
3096 mv_reset_pci_bus(host, mmio);
3218 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
3220 struct mv_host_priv *hpriv = host->private_data;
3497 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3623 struct mv_host_priv *hpriv = ap->host->private_data;
3667 struct mv_host_priv *hpriv = ap->host->private_data;
3729 static unsigned int mv_in_pcix_mode(struct ata_host *host)
3731 struct mv_host_priv *hpriv = host->private_data;
3743 static int mv_pci_cut_through_okay(struct ata_host *host)
3745 struct mv_host_priv *hpriv = host->private_data;
3749 if (!mv_in_pcix_mode(host)) {
3757 static void mv_60x1b2_errata_pci7(struct ata_host *host)
3759 struct mv_host_priv *hpriv = host->private_data;
3763 if (mv_in_pcix_mode(host)) {
3769 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
3771 struct pci_dev *pdev = to_pci_dev(host->dev);
3772 struct mv_host_priv *hpriv = host->private_data;
3822 mv_60x1b2_errata_pci7(host);
3871 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3895 dev_alert(host->dev, "BUG: invalid board index %u\n", board_idx);
3914 * mv_init_host - Perform some early initialization of the host.
3915 * @host: ATA host to initialize
3917 * If possible, do an early global reset of the host. Then do
3918 * our port init and clear/unmask all/relevant host interrupts.
3923 static int mv_init_host(struct ata_host *host)
3926 struct mv_host_priv *hpriv = host->private_data;
3929 rc = mv_chip_id(host, hpriv->board_idx);
3945 mv_set_main_irq_mask(host, ~0, 0);
3947 n_hc = mv_get_hc_count(host->ports[0]->flags);
3949 for (port = 0; port < host->n_ports; port++)
3958 hpriv->ops->reset_bus(host, mmio);
3961 for (port = 0; port < host->n_ports; port++) {
3962 struct ata_port *ap = host->ports[port];
3981 /* Clear any currently outstanding host interrupt conditions */
3984 /* and unmask interrupt generation for host regs */
3989 * enable only global host interrupts for now.
3992 mv_set_main_irq_mask(host, 0, PCI_ERR);
3993 mv_set_irq_coalescing(host, irq_coalescing_io_count,
4042 * host
4054 struct ata_host *host;
4078 /* allocate host */
4105 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4108 if (!host || !hpriv)
4120 host->private_data = hpriv;
4123 host->iomap = NULL;
4184 rc = mv_init_host(host);
4189 (unsigned)MV_MAX_Q_DEPTH, host->n_ports);
4191 rc = ata_host_activate(host, irq, mv_interrupt, IRQF_SHARED, &mv6_sht);
4221 struct ata_host *host = platform_get_drvdata(pdev);
4222 struct mv_host_priv *hpriv = host->private_data;
4224 ata_host_detach(host);
4230 for (port = 0; port < host->n_ports; port++) {
4243 struct ata_host *host = platform_get_drvdata(pdev);
4244 if (host)
4245 return ata_host_suspend(host, state);
4252 struct ata_host *host = platform_get_drvdata(pdev);
4256 if (host) {
4257 struct mv_host_priv *hpriv = host->private_data;
4267 ret = mv_init_host(host);
4272 ata_host_resume(host);
4325 * @host: ATA host to print info about
4332 static void mv_print_info(struct ata_host *host)
4334 struct pci_dev *pdev = to_pci_dev(host->dev);
4335 struct mv_host_priv *hpriv = host->private_data;
4360 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
4365 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
4367 * @ent: PCI device ID entry for the matched host
4377 struct ata_host *host;
4383 /* allocate host */
4386 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4388 if (!host || !hpriv)
4390 host->private_data = hpriv;
4404 host->iomap = pcim_iomap_table(pdev);
4405 hpriv->base = host->iomap[MV_PRIMARY_BAR];
4417 for (port = 0; port < host->n_ports; port++) {
4418 struct ata_port *ap = host->ports[port];
4427 rc = mv_init_host(host);
4436 mv_print_info(host);
4440 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
4447 struct ata_host *host = pci_get_drvdata(pdev);
4455 rc = mv_init_host(host);
4459 ata_host_resume(host);