Lines Matching defs:base
544 void __iomem *base;
890 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
892 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
895 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
898 return mv_hc_base(base, mv_hc_from_port(port));
901 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
903 return mv_hc_base_from_port(base, port) +
919 return hpriv->base;
1091 void __iomem *mmio = hpriv->base, *hc_mmio;
1151 * @base: port base address
1208 * @port_mmio: io base address
1513 old = readl(hpriv->base + GPIO_PORT_CTL);
1519 writel(new, hpriv->base + GPIO_PORT_CTL);
2886 void __iomem *mmio = hpriv->base, *hc_mmio;
3024 handled = mv_pci_error(host, hpriv->base);
3058 void __iomem *mmio = hpriv->base;
3072 void __iomem *mmio = hpriv->base;
3254 * @mmio: base address of the HBA
3542 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3625 void __iomem *mmio = hpriv->base;
3670 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
3687 * @port_mmio: base address of the port
3732 void __iomem *mmio = hpriv->base;
3746 void __iomem *mmio = hpriv->base;
3760 void __iomem *mmio = hpriv->base;
3927 void __iomem *mmio = hpriv->base;
4025 writel(0, hpriv->base + WINDOW_CTRL(i));
4026 writel(0, hpriv->base + WINDOW_BASE(i));
4035 hpriv->base + WINDOW_CTRL(i));
4036 writel(cs->base, hpriv->base + WINDOW_BASE(i));
4072 * Get the register base first
4124 hpriv->base = devm_ioremap(&pdev->dev, res->start,
4126 if (!hpriv->base)
4129 hpriv->base -= SATAHC0_REG_BASE;
4405 hpriv->base = host->iomap[MV_PRIMARY_BAR];
4419 void __iomem *port_mmio = mv_port_base(hpriv->base, port);
4420 unsigned int offset = port_mmio - hpriv->base;