Lines Matching refs:sg
126 bool gemini_sata_bridge_enabled(struct sata_gemini *sg, bool is_ata1)
128 if (!sg->sata_bridge)
134 if ((sg->muxmode == GEMINI_MUXMODE_2) &&
137 if ((sg->muxmode == GEMINI_MUXMODE_3) &&
145 enum gemini_muxmode gemini_sata_get_muxmode(struct sata_gemini *sg)
147 return sg->muxmode;
151 static int gemini_sata_setup_bridge(struct sata_gemini *sg,
161 if (sg->muxmode == GEMINI_MUXMODE_2)
163 writel(val, sg->base + GEMINI_SATA0_CTRL);
167 if (sg->muxmode == GEMINI_MUXMODE_3)
169 writel(val, sg->base + GEMINI_SATA1_CTRL);
180 val = readl(sg->base + GEMINI_SATA0_STATUS);
182 val = readl(sg->base + GEMINI_SATA1_STATUS);
189 dev_info(sg->dev, "SATA%d PHY %s\n", bridge,
195 int gemini_sata_start_bridge(struct sata_gemini *sg, unsigned int bridge)
201 pclk = sg->sata0_pclk;
203 pclk = sg->sata1_pclk;
208 ret = gemini_sata_setup_bridge(sg, bridge);
216 void gemini_sata_stop_bridge(struct sata_gemini *sg, unsigned int bridge)
219 clk_disable(sg->sata0_pclk);
221 clk_disable(sg->sata1_pclk);
225 int gemini_sata_reset_bridge(struct sata_gemini *sg,
229 reset_control_reset(sg->sata0_reset);
231 reset_control_reset(sg->sata1_reset);
233 return gemini_sata_setup_bridge(sg, bridge);
237 static int gemini_sata_bridge_init(struct sata_gemini *sg)
239 struct device *dev = sg->dev;
243 sg->sata0_pclk = devm_clk_get(dev, "SATA0_PCLK");
244 if (IS_ERR(sg->sata0_pclk)) {
248 sg->sata1_pclk = devm_clk_get(dev, "SATA1_PCLK");
249 if (IS_ERR(sg->sata1_pclk)) {
254 ret = clk_prepare_enable(sg->sata0_pclk);
259 ret = clk_prepare_enable(sg->sata1_pclk);
262 clk_disable_unprepare(sg->sata0_pclk);
266 sg->sata0_reset = devm_reset_control_get_exclusive(dev, "sata0");
267 if (IS_ERR(sg->sata0_reset)) {
269 clk_disable_unprepare(sg->sata1_pclk);
270 clk_disable_unprepare(sg->sata0_pclk);
271 return PTR_ERR(sg->sata0_reset);
273 sg->sata1_reset = devm_reset_control_get_exclusive(dev, "sata1");
274 if (IS_ERR(sg->sata1_reset)) {
276 clk_disable_unprepare(sg->sata1_pclk);
277 clk_disable_unprepare(sg->sata0_pclk);
278 return PTR_ERR(sg->sata1_reset);
281 sata_id = readl(sg->base + GEMINI_SATA_ID);
282 sata_phy_id = readl(sg->base + GEMINI_SATA_PHY_ID);
283 sg->sata_bridge = true;
284 clk_disable(sg->sata0_pclk);
285 clk_disable(sg->sata1_pclk);
319 struct sata_gemini *sg;
327 sg = devm_kzalloc(dev, sizeof(*sg), GFP_KERNEL);
328 if (!sg)
330 sg->dev = dev;
336 sg->base = devm_ioremap_resource(dev, res);
337 if (IS_ERR(sg->base))
338 return PTR_ERR(sg->base);
348 ret = gemini_sata_bridge_init(sg);
354 sg->ide_pins = true;
356 if (!sg->sata_bridge && !sg->ide_pins) {
372 sg->muxmode = muxmode;
388 if (sg->ide_pins) {
395 platform_set_drvdata(pdev, sg);
396 sg_singleton = sg;
401 if (sg->sata_bridge) {
402 clk_unprepare(sg->sata1_pclk);
403 clk_unprepare(sg->sata0_pclk);
410 struct sata_gemini *sg = platform_get_drvdata(pdev);
412 if (sg->sata_bridge) {
413 clk_unprepare(sg->sata1_pclk);
414 clk_unprepare(sg->sata0_pclk);