Lines Matching defs:hcr_base
280 void __iomem *hcr_base;
293 void __iomem *hcr_base = host_priv->hcr_base;
308 iowrite32((count << 24 | ticks), hcr_base + ICC);
317 hcr_base, ioread32(hcr_base + ICC));
389 void __iomem *hcr_base)
398 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
510 void __iomem *hcr_base = host_priv->hcr_base;
511 unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
559 void __iomem *hcr_base = host_priv->hcr_base;
560 unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
563 ioread32(CQ + hcr_base),
564 ioread32(CA + hcr_base),
565 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
567 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
570 iowrite32(1 << tag, CQ + hcr_base);
573 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
576 ioread32(CE + hcr_base),
577 ioread32(DE + hcr_base),
578 ioread32(CC + hcr_base),
588 void __iomem *hcr_base = host_priv->hcr_base;
589 unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base);
649 void __iomem *hcr_base = host_priv->hcr_base;
653 ioread32(CQ + hcr_base),
654 ioread32(CA + hcr_base),
655 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
660 temp = ioread32(hcr_base + HCONTROL);
661 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
664 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
670 void __iomem *hcr_base = host_priv->hcr_base;
674 temp = ioread32(hcr_base + HSTATUS);
679 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
682 temp = ioread32(hcr_base + HCONTROL);
683 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
686 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
692 void __iomem *hcr_base = host_priv->hcr_base;
695 temp = ioread32(hcr_base + HCONTROL);
696 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
702 void __iomem *hcr_base = host_priv->hcr_base;
705 temp = ioread32(hcr_base + HCONTROL);
707 iowrite32(temp, hcr_base + HCONTROL);
710 temp = ioread32(hcr_base + HCONTROL);
711 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
722 void __iomem *hcr_base = host_priv->hcr_base;
751 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
761 temp = ioread32(hcr_base + HCONTROL);
762 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
764 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
765 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
766 VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
776 void __iomem *hcr_base = host_priv->hcr_base;
782 temp = ioread32(hcr_base + HCONTROL);
785 iowrite32(temp, hcr_base + HCONTROL);
788 ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
800 void __iomem *hcr_base = host_priv->hcr_base;
804 temp = ioread32(hcr_base + SIGNATURE);
807 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
808 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
823 void __iomem *hcr_base = host_priv->hcr_base;
834 temp = ioread32(hcr_base + HCONTROL);
836 iowrite32(temp, hcr_base + HCONTROL);
839 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
856 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
857 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
873 temp = ioread32(hcr_base + HCONTROL);
876 iowrite32(temp, hcr_base + HCONTROL);
878 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
886 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
887 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
895 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
898 ioread32(hcr_base + HSTATUS));
907 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
937 void __iomem *hcr_base = host_priv->hcr_base;
981 ioread32(CQ + hcr_base),
982 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
984 iowrite32(0xFFFF, CC + hcr_base);
986 iowrite32(pmp, CQPMP + hcr_base);
987 iowrite32(1, CQ + hcr_base);
989 temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
994 ioread32(CQ + hcr_base),
995 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
999 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1000 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1022 iowrite32(pmp, CQPMP + hcr_base);
1023 iowrite32(1, CQ + hcr_base);
1031 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
1049 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
1050 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
1081 void __iomem *hcr_base = host_priv->hcr_base;
1089 hstatus = ioread32(hcr_base + HSTATUS);
1090 cereg = ioread32(hcr_base + CE);
1106 hstatus, cereg, ioread32(hcr_base + DE), SError);
1144 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1150 dereg = ioread32(hcr_base + DE);
1151 iowrite32(dereg, hcr_base + DE);
1152 iowrite32(cereg, hcr_base + CE);
1172 dereg = ioread32(hcr_base + DE);
1173 iowrite32(dereg, hcr_base + DE);
1174 iowrite32(cereg, hcr_base + CE);
1207 void __iomem *hcr_base = host_priv->hcr_base;
1214 hstatus = ioread32(hcr_base + HSTATUS);
1219 done_mask = ioread32(hcr_base + CC);
1227 hcontrol = ioread32(hcr_base + HCONTROL);
1229 hcr_base + HCONTROL);
1233 hcr_base + HCONTROL);
1261 ioread32(hcr_base + CA),
1262 ioread32(hcr_base + CE),
1263 ioread32(hcr_base + CQ),
1269 iowrite32(done_mask, hcr_base + CC);
1273 done_mask, ioread32(hcr_base + CA),
1274 ioread32(hcr_base + CE));
1280 i, ioread32(hcr_base + CC),
1281 ioread32(hcr_base + CA));
1287 iowrite32(1, hcr_base + CC);
1291 ioread32(hcr_base + CC));
1299 ioread32(hcr_base + CC));
1300 iowrite32(done_mask, hcr_base + CC);
1309 void __iomem *hcr_base = host_priv->hcr_base;
1315 interrupt_enables = ioread32(hcr_base + HSTATUS);
1334 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1349 void __iomem *hcr_base = host_priv->hcr_base;
1359 temp = ioread32(hcr_base + HCONTROL);
1360 iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL);
1363 temp = ioread32(hcr_base + HSTATUS);
1365 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1368 temp = ioread32(hcr_base + HCONTROL);
1369 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1372 DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1373 iowrite32(0x01000000, hcr_base + ICC);
1376 iowrite32(0x00000FFFF, hcr_base + CE);
1377 iowrite32(0x00000FFFF, hcr_base + DE);
1391 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1392 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1401 iounmap(host_priv->hcr_base);
1455 void __iomem *hcr_base = NULL;
1468 hcr_base = of_iomap(ofdev->dev.of_node, 0);
1469 if (!hcr_base)
1472 ssr_base = hcr_base + 0x100;
1473 csr_base = hcr_base + 0x140;
1489 host_priv->hcr_base = hcr_base;
1553 if (hcr_base)
1554 iounmap(hcr_base);
1585 void __iomem *hcr_base = host_priv->hcr_base;
1596 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
1598 iowrite32((ioread32(hcr_base + HCONTROL)
1602 hcr_base + HCONTROL);