Lines Matching refs:mmio_base
473 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
479 bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
480 bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
483 bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
484 bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
514 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
533 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
573 iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL);
574 ioread16(mmio_base + PDC_PLL_CTL); /* flush */
584 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
600 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
607 scr = ioread32(mmio_base + PDC_SYS_CTL);
609 iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
610 ioread32(mmio_base + PDC_SYS_CTL); /* flush */
624 scr = ioread32(mmio_base + PDC_SYS_CTL);
626 iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
627 ioread32(mmio_base + PDC_SYS_CTL); /* flush */
705 void __iomem *mmio_base;
729 mmio_base = host->iomap[PDC_MMIO_BAR];
734 pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]);
735 ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i];