Lines Matching refs:cf_port
131 struct octeon_cf_port *cf_port = ap->private_data;
170 octeon_cf_set_boot_reg_cfg(cf_port->cs0, div);
171 if (cf_port->is_true_ide)
173 octeon_cf_set_boot_reg_cfg(cf_port->cs1, div);
178 reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0));
207 cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0), reg_tim.u64);
208 if (cf_port->is_true_ide)
210 cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs1),
216 struct octeon_cf_port *cf_port = ap->private_data;
252 c = (cf_port->dma_base & 8) >> 3;
282 cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64);
543 struct octeon_cf_port *cf_port;
545 cf_port = ap->private_data;
549 cf_port->dma_finished = 0;
561 struct octeon_cf_port *cf_port = qc->ap->private_data;
577 cvmx_write_csr(cf_port->dma_base + DMA_INT, mio_boot_dma_int.u64);
580 cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, mio_boot_dma_int.u64);
612 cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64);
625 struct octeon_cf_port *cf_port = ap->private_data;
637 dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
647 cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
651 cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
655 cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
674 struct octeon_cf_port *cf_port;
690 cf_port = ap->private_data;
692 dma_int.u64 = cvmx_read_csr(cf_port->dma_base + DMA_INT);
693 dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
707 cf_port->dma_finished = 1;
710 if (!cf_port->dma_finished)
723 cvmx_write_csr(cf_port->dma_base + DMA_INT,
725 hrtimer_start_range_ns(&cf_port->delayed_finish,
741 struct octeon_cf_port *cf_port = container_of(hrt,
744 struct ata_port *ap = cf_port->ap;
758 if (ap->hsm_task_state != HSM_ST_LAST || !cf_port->dma_finished)
850 struct octeon_cf_port *cf_port;
858 cf_port = devm_kzalloc(&pdev->dev, sizeof(*cf_port), GFP_KERNEL);
859 if (!cf_port)
862 cf_port->is_true_ide = of_property_read_bool(node, "cavium,true-ide");
877 cf_port->cs0 = be32_to_cpup(cs_num);
879 if (cf_port->is_true_ide) {
895 cf_port->dma_base = (u64)devm_ioremap(&pdev->dev, res_dma->start,
897 if (!cf_port->dma_base) {
925 cf_port->cs1 = be32_to_cpup(cs_num);
943 ap->private_data = cf_port;
944 pdev->dev.platform_data = cf_port;
945 cf_port->ap = ap;
958 } else if (cf_port->is_true_ide) {
978 hrtimer_init(&cf_port->delayed_finish, CLOCK_MONOTONIC,
980 cf_port->delayed_finish.function = octeon_cf_delayed_finish;
997 cf_port->c0 = ap->ioaddr.ctl_addr;
1007 cf_port->is_true_ide ? ", True IDE" : "");
1018 struct octeon_cf_port *cf_port = dev_get_platdata(dev);
1020 if (cf_port->dma_base) {
1024 cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
1028 cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64);
1032 cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64);
1034 __raw_writeb(0, cf_port->c0);
1036 __raw_writeb(ATA_SRST, cf_port->c0);
1038 __raw_writeb(0, cf_port->c0);