Lines Matching defs:timing
85 unsigned long timing;
355 /* Get the timing data in cycles. For now play safe at 50Mhz */
389 /* Get the timing data in cycles. For now play safe at 50Mhz */
465 /* Get the timing data in cycles */
468 /* Setup timing is shared */
480 /* Select the right timing bank for write timing */
500 /* Ensure the timing register mode is right */
544 /* Get the timing data in cycles */
547 /* Setup timing is shared */
559 /* Select the right timing bank for write timing */
579 /* Ensure the timing register mode is right */
598 * MVB has a single set of timing registers and these are shared
633 * avoid the requirement to clock switch. We also have to load the timing
645 u8 timing;
647 /* Get the timing data in cycles */
657 timing = (recovery << 4) | active | 0x08;
658 ld_qdi->clock[adev->devno] = timing;
661 outb(timing, ld_qdi->timing + 2 * adev->devno);
663 outb(timing, ld_qdi->timing + 2 * ap->port_no);
667 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);
687 outb(ld_qdi->clock[adev->devno], ld_qdi->timing +
730 ld->timing = lp->private;
784 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
786 reg = winbond_readcfg(ld_winbond->timing, 0x81);
788 /* Get the timing data in cycles */
796 timing = (active << 4) | recovery;
797 winbond_writecfg(ld_winbond->timing, timing, reg);
799 /* Load the setup timing */
807 winbond_writecfg(ld_winbond->timing, timing + 1, reg);
815 ld->timing = lp->private;
873 reg |= 0xF0; /* programmable timing */