Lines Matching refs:timreg
149 u8 timreg;
173 timreg = udma_66_setup_time[i] << 4 |
176 timreg = udma_50_setup_time[i] << 4 |
182 timreg |= FTIDE010_UDMA_TIMING_MODE_56;
184 dev_dbg(ftide->dev, "UDMA write clkreg = %02x, timreg = %02x\n",
185 clkreg, timreg);
188 writeb(timreg, ftide->base + FTIDE010_UDMA_TIMING0 + devno);
196 timreg = mwdma_66_active_time[i] << 4 |
199 timreg = mwdma_50_active_time[i] << 4 |
203 "MWDMA write clkreg = %02x, timreg = %02x\n",
204 clkreg, timreg);
207 writeb(timreg, ftide->base + FTIDE010_MWDMA_TIMING);