Lines Matching defs:drv_data
262 static u16 ep93xx_pata_read(struct ep93xx_pata_data *drv_data,
266 void __iomem *base = drv_data->ide_base;
267 const struct ata_timing *t = &drv_data->t;
278 ep93xx_pata_rw_end(base, addr, drv_data->iordy, t0, t2, t2i);
283 static u16 ep93xx_pata_read_reg(struct ep93xx_pata_data *drv_data,
286 return ep93xx_pata_read(drv_data, addr, true);
290 static u16 ep93xx_pata_read_data(struct ep93xx_pata_data *drv_data,
293 return ep93xx_pata_read(drv_data, addr, false);
296 static void ep93xx_pata_write(struct ep93xx_pata_data *drv_data,
300 void __iomem *base = drv_data->ide_base;
301 const struct ata_timing *t = &drv_data->t;
313 ep93xx_pata_rw_end(base, addr, drv_data->iordy, t0, t2, t2i);
317 static void ep93xx_pata_write_reg(struct ep93xx_pata_data *drv_data,
320 ep93xx_pata_write(drv_data, value, addr, true);
324 static void ep93xx_pata_write_data(struct ep93xx_pata_data *drv_data,
327 ep93xx_pata_write(drv_data, value, addr, false);
333 struct ep93xx_pata_data *drv_data = ap->host->private_data;
344 ata_timing_compute(adev, adev->pio_mode, &drv_data->t, T, 0);
348 ata_timing_merge(&t, &drv_data->t, &drv_data->t,
351 drv_data->iordy = ata_pio_need_iordy(adev);
353 ep93xx_pata_enable_pio(drv_data->ide_base,
360 struct ep93xx_pata_data *drv_data = ap->host->private_data;
362 return ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_STATUS);
367 struct ep93xx_pata_data *drv_data = ap->host->private_data;
369 return ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_ALTSTATUS);
376 struct ep93xx_pata_data *drv_data = ap->host->private_data;
380 ep93xx_pata_write_reg(drv_data, tf->ctl, IDECTRL_ADDR_CTL);
386 ep93xx_pata_write_reg(drv_data, tf->hob_feature,
388 ep93xx_pata_write_reg(drv_data, tf->hob_nsect,
390 ep93xx_pata_write_reg(drv_data, tf->hob_lbal,
392 ep93xx_pata_write_reg(drv_data, tf->hob_lbam,
394 ep93xx_pata_write_reg(drv_data, tf->hob_lbah,
399 ep93xx_pata_write_reg(drv_data, tf->feature,
401 ep93xx_pata_write_reg(drv_data, tf->nsect, IDECTRL_ADDR_NSECT);
402 ep93xx_pata_write_reg(drv_data, tf->lbal, IDECTRL_ADDR_LBAL);
403 ep93xx_pata_write_reg(drv_data, tf->lbam, IDECTRL_ADDR_LBAM);
404 ep93xx_pata_write_reg(drv_data, tf->lbah, IDECTRL_ADDR_LBAH);
408 ep93xx_pata_write_reg(drv_data, tf->device,
417 struct ep93xx_pata_data *drv_data = ap->host->private_data;
420 tf->feature = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_FEATURE);
421 tf->nsect = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_NSECT);
422 tf->lbal = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAL);
423 tf->lbam = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAM);
424 tf->lbah = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAH);
425 tf->device = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_DEVICE);
428 ep93xx_pata_write_reg(drv_data, tf->ctl | ATA_HOB,
430 tf->hob_feature = ep93xx_pata_read_reg(drv_data,
432 tf->hob_nsect = ep93xx_pata_read_reg(drv_data,
434 tf->hob_lbal = ep93xx_pata_read_reg(drv_data,
436 tf->hob_lbam = ep93xx_pata_read_reg(drv_data,
438 tf->hob_lbah = ep93xx_pata_read_reg(drv_data,
440 ep93xx_pata_write_reg(drv_data, tf->ctl, IDECTRL_ADDR_CTL);
449 struct ep93xx_pata_data *drv_data = ap->host->private_data;
451 ep93xx_pata_write_reg(drv_data, tf->command,
459 struct ep93xx_pata_data *drv_data = ap->host->private_data;
465 ep93xx_pata_write_reg(drv_data, tmp, IDECTRL_ADDR_DEVICE);
472 struct ep93xx_pata_data *drv_data = ap->host->private_data;
474 ep93xx_pata_write_reg(drv_data, ctl, IDECTRL_ADDR_CTL);
483 struct ep93xx_pata_data *drv_data = ap->host->private_data;
492 drv_data, IDECTRL_ADDR_DATA));
494 ep93xx_pata_write_data(drv_data, le16_to_cpu(*data++),
506 drv_data, IDECTRL_ADDR_DATA));
510 ep93xx_pata_write_data(drv_data, le16_to_cpu(*pad),
523 struct ep93xx_pata_data *drv_data = ap->host->private_data;
528 ep93xx_pata_write_reg(drv_data, 0x55, IDECTRL_ADDR_NSECT);
529 ep93xx_pata_write_reg(drv_data, 0xaa, IDECTRL_ADDR_LBAL);
531 ep93xx_pata_write_reg(drv_data, 0xaa, IDECTRL_ADDR_NSECT);
532 ep93xx_pata_write_reg(drv_data, 0x55, IDECTRL_ADDR_LBAL);
534 ep93xx_pata_write_reg(drv_data, 0x55, IDECTRL_ADDR_NSECT);
535 ep93xx_pata_write_reg(drv_data, 0xaa, IDECTRL_ADDR_LBAL);
537 nsect = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_NSECT);
538 lbal = ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_LBAL);
552 struct ep93xx_pata_data *drv_data = ap->host->private_data;
585 nsect = ep93xx_pata_read_reg(drv_data,
587 lbal = ep93xx_pata_read_reg(drv_data,
615 struct ep93xx_pata_data *drv_data = ap->host->private_data;
617 ep93xx_pata_write_reg(drv_data, ap->ctl, IDECTRL_ADDR_CTL);
619 ep93xx_pata_write_reg(drv_data, ap->ctl | ATA_SRST, IDECTRL_ADDR_CTL);
621 ep93xx_pata_write_reg(drv_data, ap->ctl, IDECTRL_ADDR_CTL);
627 static void ep93xx_pata_release_dma(struct ep93xx_pata_data *drv_data)
629 if (drv_data->dma_rx_channel) {
630 dma_release_channel(drv_data->dma_rx_channel);
631 drv_data->dma_rx_channel = NULL;
633 if (drv_data->dma_tx_channel) {
634 dma_release_channel(drv_data->dma_tx_channel);
635 drv_data->dma_tx_channel = NULL;
648 static void ep93xx_pata_dma_init(struct ep93xx_pata_data *drv_data)
650 const struct platform_device *pdev = drv_data->pdev;
662 drv_data->dma_rx_data.port = EP93XX_DMA_IDE;
663 drv_data->dma_rx_data.direction = DMA_DEV_TO_MEM;
664 drv_data->dma_rx_data.name = "ep93xx-pata-rx";
665 drv_data->dma_rx_channel = dma_request_channel(mask,
666 ep93xx_pata_dma_filter, &drv_data->dma_rx_data);
667 if (!drv_data->dma_rx_channel)
670 drv_data->dma_tx_data.port = EP93XX_DMA_IDE;
671 drv_data->dma_tx_data.direction = DMA_MEM_TO_DEV;
672 drv_data->dma_tx_data.name = "ep93xx-pata-tx";
673 drv_data->dma_tx_channel = dma_request_channel(mask,
674 ep93xx_pata_dma_filter, &drv_data->dma_tx_data);
675 if (!drv_data->dma_tx_channel) {
676 dma_release_channel(drv_data->dma_rx_channel);
683 conf.src_addr = drv_data->udma_in_phys;
685 if (dmaengine_slave_config(drv_data->dma_rx_channel, &conf)) {
687 ep93xx_pata_release_dma(drv_data);
694 conf.dst_addr = drv_data->udma_out_phys;
696 if (dmaengine_slave_config(drv_data->dma_tx_channel, &conf)) {
698 ep93xx_pata_release_dma(drv_data);
705 struct ep93xx_pata_data *drv_data = qc->ap->host->private_data;
706 void __iomem *base = drv_data->ide_base;
710 ? drv_data->dma_tx_channel : drv_data->dma_rx_channel;
745 struct ep93xx_pata_data *drv_data = qc->ap->host->private_data;
746 void __iomem *base = drv_data->ide_base;
749 dmaengine_terminate_all(drv_data->dma_rx_channel);
750 dmaengine_terminate_all(drv_data->dma_tx_channel);
760 ep93xx_pata_enable_pio(drv_data->ide_base,
773 struct ep93xx_pata_data *drv_data = ap->host->private_data;
774 u32 val = readl(drv_data->ide_base + IDEUDMASTS);
794 if (readl(drv_data->ide_base + IDECTRL) & IDECTRL_INTRQ)
845 struct ep93xx_pata_data *drv_data;
852 drv_data = ap->host->private_data;
856 ep93xx_pata_read_reg(drv_data, IDECTRL_ADDR_DATA);
866 struct ep93xx_pata_data *drv_data = ap->host->private_data;
872 drv_data->t = *ata_timing_find_mode(XFER_PIO_0);
916 struct ep93xx_pata_data *drv_data;
942 drv_data = devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL);
943 if (!drv_data) {
948 drv_data->pdev = pdev;
949 drv_data->ide_base = ide_base;
950 drv_data->udma_in_phys = mem_res->start + IDEUDMADATAIN;
951 drv_data->udma_out_phys = mem_res->start + IDEUDMADATAOUT;
952 ep93xx_pata_dma_init(drv_data);
963 host->private_data = drv_data;
980 if (drv_data->dma_rx_channel && drv_data->dma_tx_channel) {
1003 ep93xx_pata_release_dma(drv_data);
1012 struct ep93xx_pata_data *drv_data = host->private_data;
1015 ep93xx_pata_release_dma(drv_data);
1016 ep93xx_pata_clear_regs(drv_data->ide_base);