Lines Matching refs:vbase
194 void __iomem *vbase;
230 dev_dbg(dev, ": CFI_STS: %x", readl(acdev->vbase + CFI_STS));
231 dev_dbg(dev, ": IRQ_STS: %x", readl(acdev->vbase + IRQ_STS));
232 dev_dbg(dev, ": IRQ_EN: %x", readl(acdev->vbase + IRQ_EN));
233 dev_dbg(dev, ": OP_MODE: %x", readl(acdev->vbase + OP_MODE));
234 dev_dbg(dev, ": CLK_CFG: %x", readl(acdev->vbase + CLK_CFG));
235 dev_dbg(dev, ": TM_CFG: %x", readl(acdev->vbase + TM_CFG));
236 dev_dbg(dev, ": XFER_CTR: %x", readl(acdev->vbase + XFER_CTR));
237 dev_dbg(dev, ": GIRQ_STS: %x", readl(acdev->vbase + GIRQ_STS));
238 dev_dbg(dev, ": GIRQ_STS_EN: %x", readl(acdev->vbase + GIRQ_STS_EN));
239 dev_dbg(dev, ": GIRQ_SGN_EN: %x", readl(acdev->vbase + GIRQ_SGN_EN));
247 writel(enable, acdev->vbase + GIRQ_STS_EN);
248 writel(enable, acdev->vbase + GIRQ_SGN_EN);
255 u32 val = readl(acdev->vbase + IRQ_EN);
258 writel(mask, acdev->vbase + IRQ_STS);
259 writel(val | mask, acdev->vbase + IRQ_EN);
261 writel(val & ~mask, acdev->vbase + IRQ_EN);
266 u32 val = readl(acdev->vbase + OP_MODE);
268 writel(val | CARD_RESET, acdev->vbase + OP_MODE);
270 writel(val & ~CARD_RESET, acdev->vbase + OP_MODE);
275 writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB,
276 acdev->vbase + OP_MODE);
277 writel(readl(acdev->vbase + OP_MODE) | CFHOST_ENB,
278 acdev->vbase + OP_MODE);
285 u32 val = readl(acdev->vbase + CFI_STS);
332 writel(if_clk, acdev->vbase + CLK_CFG);
334 writel(TRUE_IDE_MODE | CFHOST_ENB, acdev->vbase + OP_MODE);
350 writel(readl(acdev->vbase + OP_MODE) & ~CFHOST_ENB,
351 acdev->vbase + OP_MODE);
457 xfer_ctr = readl(acdev->vbase + XFER_CTR) &
460 acdev->vbase + XFER_CTR);
499 writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
500 acdev->vbase + XFER_CTR);
599 irqsts = readl(acdev->vbase + GIRQ_STS);
604 irqsts = readl(acdev->vbase + IRQ_STS);
605 writel(irqsts, acdev->vbase + IRQ_STS); /* clear irqs */
606 writel(GIRQ_CF, acdev->vbase + GIRQ_STS); /* clear girqs */
619 writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
620 acdev->vbase + XFER_CTR);
650 writel(readl(acdev->vbase + XFER_CTR) & ~XFER_START,
651 acdev->vbase + XFER_CTR);
678 u32 xfer_ctr = readl(acdev->vbase + XFER_CTR) & ~XFER_DIR_MASK;
682 writel(xfer_ctr, acdev->vbase + XFER_CTR);
736 val = readl(acdev->vbase + OP_MODE) &
738 writel(val, acdev->vbase + OP_MODE);
739 val = readl(acdev->vbase + TM_CFG) & ~TRUEIDE_PIO_TIMING_MASK;
741 writel(val, acdev->vbase + TM_CFG);
755 opmode = readl(acdev->vbase + OP_MODE) &
757 tmcfg = readl(acdev->vbase + TM_CFG);
774 writel(opmode, acdev->vbase + OP_MODE);
775 writel(tmcfg, acdev->vbase + TM_CFG);
776 writel(DMA_XFER_MODE, acdev->vbase + XFER_CTR);
837 acdev->vbase = devm_ioremap(&pdev->dev, res->start,
839 if (!acdev->vbase) {
884 ap->ioaddr.cmd_addr = acdev->vbase + ATA_DATA_PORT;
885 ap->ioaddr.data_addr = acdev->vbase + ATA_DATA_PORT;
886 ap->ioaddr.error_addr = acdev->vbase + ATA_ERR_FTR;
887 ap->ioaddr.feature_addr = acdev->vbase + ATA_ERR_FTR;
888 ap->ioaddr.nsect_addr = acdev->vbase + ATA_SC;
889 ap->ioaddr.lbal_addr = acdev->vbase + ATA_SN;
890 ap->ioaddr.lbam_addr = acdev->vbase + ATA_CL;
891 ap->ioaddr.lbah_addr = acdev->vbase + ATA_CH;
892 ap->ioaddr.device_addr = acdev->vbase + ATA_SH;
893 ap->ioaddr.status_addr = acdev->vbase + ATA_STS_CMD;
894 ap->ioaddr.command_addr = acdev->vbase + ATA_STS_CMD;
895 ap->ioaddr.altstatus_addr = acdev->vbase + ATA_ASTS_DCTR;
896 ap->ioaddr.ctl_addr = acdev->vbase + ATA_ASTS_DCTR;
899 (unsigned long long) res->start, acdev->vbase);