Lines Matching defs:port_mmio
273 void __iomem *port_mmio = ahci_port_base(ap);
277 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
600 void __iomem *port_mmio = ahci_port_base(link->ap);
604 *val = readl(port_mmio + offset);
612 void __iomem *port_mmio = ahci_port_base(link->ap);
616 writel(val, port_mmio + offset);
624 void __iomem *port_mmio = ahci_port_base(ap);
628 tmp = readl(port_mmio + PORT_CMD);
630 writel(tmp, port_mmio + PORT_CMD);
631 readl(port_mmio + PORT_CMD); /* flush */
637 void __iomem *port_mmio = ahci_port_base(ap);
654 tmp = readl(port_mmio + PORT_CMD);
672 writel(tmp, port_mmio + PORT_CMD);
675 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
686 void __iomem *port_mmio = ahci_port_base(ap);
694 port_mmio + PORT_LST_ADDR_HI);
695 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
699 port_mmio + PORT_FIS_ADDR_HI);
700 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
703 tmp = readl(port_mmio + PORT_CMD);
705 writel(tmp, port_mmio + PORT_CMD);
708 readl(port_mmio + PORT_CMD);
714 void __iomem *port_mmio = ahci_port_base(ap);
718 tmp = readl(port_mmio + PORT_CMD);
720 writel(tmp, port_mmio + PORT_CMD);
723 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
734 void __iomem *port_mmio = ahci_port_base(ap);
737 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
742 writel(cmd, port_mmio + PORT_CMD);
746 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
755 void __iomem *port_mmio = ahci_port_base(ap);
767 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
773 u32 cmd = readl(port_mmio + PORT_CMD);
780 writel(cmd, port_mmio + PORT_CMD);
781 readl(port_mmio + PORT_CMD);
796 writel(cmd, port_mmio + PORT_CMD);
816 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
826 void __iomem *port_mmio = ahci_port_base(ap);
833 scontrol = readl(port_mmio + PORT_SCR_CTL);
835 writel(scontrol, port_mmio + PORT_SCR_CTL);
838 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
840 writel(cmd, port_mmio + PORT_CMD);
1205 void __iomem *port_mmio = ahci_port_base(ap);
1209 tmp = readl(port_mmio + PORT_SCR_ERR);
1211 writel(tmp, port_mmio + PORT_SCR_ERR);
1214 tmp = readl(port_mmio + PORT_IRQ_STAT);
1217 writel(tmp, port_mmio + PORT_IRQ_STAT);
1224 void __iomem *port_mmio)
1239 tmp = readl(port_mmio + PORT_CMD);
1249 void __iomem *port_mmio;
1255 port_mmio = ahci_port_base(ap);
1259 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1283 void __iomem *port_mmio = ahci_port_base(ap);
1287 tmp = readl(port_mmio + PORT_SIG);
1313 void __iomem *port_mmio = ahci_port_base(ap);
1315 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1339 tmp = readl(port_mmio + PORT_CMD);
1341 writel(tmp, port_mmio + PORT_CMD);
1344 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1362 void __iomem *port_mmio = ahci_port_base(ap);
1372 tmp = readl(port_mmio + PORT_FBS);
1375 writel(tmp, port_mmio + PORT_FBS);
1380 writel(1, port_mmio + PORT_CMD_ISSUE);
1383 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1390 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1479 void __iomem *port_mmio = ahci_port_base(link->ap);
1480 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1499 void __iomem *port_mmio = ahci_port_base(link->ap);
1500 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1501 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1517 void __iomem *port_mmio = ahci_port_base(ap);
1533 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1592 void __iomem *port_mmio = ahci_port_base(ap);
1598 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1604 writel(new_tmp, port_mmio + PORT_CMD);
1605 readl(port_mmio + PORT_CMD); /* flush */
1686 void __iomem *port_mmio = ahci_port_base(ap);
1687 u32 fbs = readl(port_mmio + PORT_FBS);
1696 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1697 fbs = readl(port_mmio + PORT_FBS);
1700 fbs = readl(port_mmio + PORT_FBS);
1720 void __iomem *port_mmio = ahci_port_base(ap);
1721 u32 fbs = readl(port_mmio + PORT_FBS);
1819 void __iomem *port_mmio, u32 status)
1880 qc_active = readl(port_mmio + PORT_SCR_ACT);
1881 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1886 qc_active = readl(port_mmio + PORT_SCR_ACT);
1888 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1904 void __iomem *port_mmio = ahci_port_base(ap);
1907 status = readl(port_mmio + PORT_IRQ_STAT);
1908 writel(status, port_mmio + PORT_IRQ_STAT);
1910 ahci_handle_port_interrupt(ap, port_mmio, status);
1916 void __iomem *port_mmio = ahci_port_base(ap);
1919 status = readl(port_mmio + PORT_IRQ_STAT);
1920 writel(status, port_mmio + PORT_IRQ_STAT);
1923 ahci_handle_port_interrupt(ap, port_mmio, status);
1996 void __iomem *port_mmio = ahci_port_base(ap);
2006 writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT);
2009 u32 fbs = readl(port_mmio + PORT_FBS);
2012 writel(fbs, port_mmio + PORT_FBS);
2016 writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE);
2050 void __iomem *port_mmio = ahci_port_base(ap);
2053 writel(0, port_mmio + PORT_IRQ_MASK);
2060 void __iomem *port_mmio = ahci_port_base(ap);
2065 tmp = readl(port_mmio + PORT_IRQ_STAT);
2066 writel(tmp, port_mmio + PORT_IRQ_STAT);
2070 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2102 void __iomem *port_mmio = ahci_port_base(ap);
2108 devslp = readl(port_mmio + PORT_DEVSLP);
2118 port_mmio + PORT_DEVSLP);
2167 writel(devslp, port_mmio + PORT_DEVSLP);
2183 void __iomem *port_mmio = ahci_port_base(ap);
2190 fbs = readl(port_mmio + PORT_FBS);
2201 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2202 fbs = readl(port_mmio + PORT_FBS);
2217 void __iomem *port_mmio = ahci_port_base(ap);
2224 fbs = readl(port_mmio + PORT_FBS);
2234 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2235 fbs = readl(port_mmio + PORT_FBS);
2248 void __iomem *port_mmio = ahci_port_base(ap);
2252 cmd = readl(port_mmio + PORT_CMD);
2254 writel(cmd, port_mmio + PORT_CMD);
2269 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2274 void __iomem *port_mmio = ahci_port_base(ap);
2280 cmd = readl(port_mmio + PORT_CMD);
2282 writel(cmd, port_mmio + PORT_CMD);
2288 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2351 void __iomem *port_mmio = ahci_port_base(ap);
2352 u32 cmd = readl(port_mmio + PORT_CMD);