Lines Matching refs:ctx
91 static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx)
93 dev_dbg(ctx->dev, "Release memory from shutdown\n");
94 writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN);
95 readl(ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */
97 if (readl(ctx->csr_diag + BLOCK_MEM_RDY) != 0xFFFFFFFF) {
98 dev_err(ctx->dev, "failed to release memory from shutdown\n");
193 struct xgene_ahci_context *ctx = hpriv->plat_data;
202 if (ctx->class[ap->port_no] == ATA_DEV_PMP) {
209 if (unlikely((ctx->last_cmd[ap->port_no] == ATA_CMD_ID_ATA) ||
210 (ctx->last_cmd[ap->port_no] == ATA_CMD_PACKET) ||
211 (ctx->last_cmd[ap->port_no] == ATA_CMD_SMART)))
217 ctx->last_cmd[ap->port_no] = qc->tf.command;
222 static bool xgene_ahci_is_memram_inited(struct xgene_ahci_context *ctx)
224 void __iomem *diagcsr = ctx->csr_diag;
267 static void xgene_ahci_set_phy_cfg(struct xgene_ahci_context *ctx, int channel)
269 void __iomem *mmio = ctx->hpriv->mmio;
272 dev_dbg(ctx->dev, "port configure mmio 0x%p channel %d\n",
356 struct xgene_ahci_context *ctx = hpriv->plat_data;
375 dev_warn(ctx->dev, "link has error\n");
501 struct xgene_ahci_context *ctx = hpriv->plat_data;
523 ctx->class[ap->port_no] = *class;
649 struct xgene_ahci_context *ctx = hpriv->plat_data;
655 rc = xgene_ahci_init_memram(ctx);
660 xgene_ahci_set_phy_cfg(ctx, i);
665 writel(0, ctx->csr_core + INTSTATUSMASK);
666 val = readl(ctx->csr_core + INTSTATUSMASK); /* Force a barrier */
667 dev_dbg(ctx->dev, "top level interrupt mask 0x%X value 0x%08X\n",
670 writel(0x0, ctx->csr_core + ERRINTSTATUSMASK);
671 readl(ctx->csr_core + ERRINTSTATUSMASK); /* Force a barrier */
672 writel(0x0, ctx->csr_axi + INT_SLV_TMOMASK);
673 readl(ctx->csr_axi + INT_SLV_TMOMASK);
676 writel(0xffffffff, ctx->csr_core + SLVRDERRATTRIBUTES);
677 writel(0xffffffff, ctx->csr_core + SLVWRERRATTRIBUTES);
678 writel(0xffffffff, ctx->csr_core + MSTRDERRATTRIBUTES);
679 writel(0xffffffff, ctx->csr_core + MSTWRERRATTRIBUTES);
682 val = readl(ctx->csr_core + BUSCTLREG);
685 writel(val, ctx->csr_core + BUSCTLREG);
687 val = readl(ctx->csr_core + IOFMSTRWAUX);
690 writel(val, ctx->csr_core + IOFMSTRWAUX);
691 val = readl(ctx->csr_core + IOFMSTRWAUX);
692 dev_dbg(ctx->dev, "coherency 0x%X value 0x%08X\n",
698 static int xgene_ahci_mux_select(struct xgene_ahci_context *ctx)
703 if (!ctx->csr_mux)
706 val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
708 writel(val, ctx->csr_mux + SATA_ENET_CONFIG_REG);
709 val = readl(ctx->csr_mux + SATA_ENET_CONFIG_REG);
737 struct xgene_ahci_context *ctx;
749 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
750 if (!ctx)
753 hpriv->plat_data = ctx;
754 ctx->hpriv = hpriv;
755 ctx->dev = dev;
759 ctx->csr_core = devm_ioremap_resource(dev, res);
760 if (IS_ERR(ctx->csr_core))
761 return PTR_ERR(ctx->csr_core);
765 ctx->csr_diag = devm_ioremap_resource(dev, res);
766 if (IS_ERR(ctx->csr_diag))
767 return PTR_ERR(ctx->csr_diag);
771 ctx->csr_axi = devm_ioremap_resource(dev, res);
772 if (IS_ERR(ctx->csr_axi))
773 return PTR_ERR(ctx->csr_axi);
782 ctx->csr_mux = csr;
816 dev_dbg(dev, "VAddr 0x%p Mmio VAddr 0x%p\n", ctx->csr_core,
820 if ((rc = xgene_ahci_mux_select(ctx))) {
825 if (xgene_ahci_is_memram_inited(ctx)) {